Per Larsson-Edefors
Per Larsson-Edefors
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A high-speed, energy-efficient two-cycle multiply-accumulate (MAC) architecture and its application to a double-throughput MAC unit
TT Hoang, M Själander, P Larsson-Edefors
IEEE Transactions on Circuits and Systems I: Regular Papers 57 (12), 3073-3081, 2010
FlexCore: Utilizing exposed datapath control for efficient computing
M Thuresson, M Själander, M Björk, L Svensson, P Larsson-Edefors, ...
Journal of Signal Processing Systems 57, 5-19, 2009
Multiplication acceleration through twin precision
M Sjalander, P Larsson-Edefors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17 (9 …, 2009
High-speed and low-power multipliers using the Baugh-Wooley algorithm and HPM reduction tree
M Sjalander, P Larsson-Edefors
2008 15th IEEE international conference on electronics, circuits and systems …, 2008
A leakage-tolerant multi-phase keeper for wide domino circuits
A Alvandpour, P Larsson-Edefors, C Svensson
ICECS'99. Proceedings of ICECS'99. 6th IEEE International Conference on …, 1999
Full-custom vs. standard-cell design flow: an adder case study
H Eriksson, P Larsson-Edefors, T Henriksson, C Svensson
Proceedings of the 2003 Asia and South Pacific Design Automation Conference …, 2003
Multiplier reduction tree with logarithmic logic depth and regular connectivity
H Eriksson, P Larsson-Edefors, M Sheeran, M Sjalander, D Johansson, ...
2006 IEEE International Symposium on Circuits and Systems, 4 pp.-8, 2006
Low-power 400-Gbps soft-decision LDPC FEC for optical transport networks
K Cushon, P Larsson-Edefors, P Andrekson
Journal of Lightwave Technology 34 (18), 4304-4311, 2016
The case for HPM-based baugh-wooley multipliers
M Själander, P Larsson-Edefors
Chalmers University of Technology, 2008
An efficient twin-precision multiplier
M Sjalander, H Eriksson, P Larsson-Edefors
IEEE International Conference on Computer Design: VLSI in Computers and …, 2004
Assessing scrubbing techniques for Xilinx SRAM-based FPGAs in space applications
F Brosser, E Milh, V Geijer, P Larsson-Edefors
2014 International Conference on Field-Programmable Technology (FPT), 296-299, 2014
A low-leakage twin-precision multiplier using reconfigurable power gating
M Sjalander, M Drazdziulis, P Larsson-Edefors, H Eriksson
2005 IEEE International Symposium on Circuits and Systems (ISCAS), 1654-1657, 2005
Parameterizable architecture-level SRAM power model using circuit-simulation backend for leakage calibration
MQ Do, M Drazdziulis, P Larsson-Edefors, L Bengtsson
7th International Symposium on Quality Electronic Design (ISQED'06), 7 pp.-563, 2006
Time-domain digital back propagation: Algorithm and finite-precision implementation aspects
C Fougstedt, M Mazur, L Svensson, H Eliasson, M Karlsson, ...
Optical Fiber Communication Conference, W1G. 4, 2017
Considerations on the use of digital signal processing in future optical access networks
LA Neto, J Maes, P Larsson-Edefors, J Nakagawa, K Onohara, ...
Journal of Lightwave Technology 38 (3), 598-607, 2020
A gate leakage reduction strategy for future CMOS circuits
M Drazdziulis, P Larsson-Edefors
ESSCIRC 2004-29th European Solid-State Circuits Conference (IEEE Cat. No …, 2003
Energy-efficient high-throughput VLSI architectures for product-like codes
C Fougstedt, P Larsson-Edefors
Journal of Lightwave Technology 37 (2), 477-485, 2019
Dispersion compensation FIR filter with improved robustness to coefficient quantization errors
A Sheikh, C Fougstedt, AG i Amat, P Johannisson, P Larsson-Edefors, ...
Journal of Lightwave Technology 34 (22), 5110-5117, 2016
Separation and extraction of short-circuit power consumption in digital CMOS VLSI circuits
A Alvandpour, P Larsson-Edefors, C Svensson
Proceedings of the 1998 international symposium on Low power electronics and …, 1998
FlexSoC: Combining flexibility and efficiency in SoC designs
J Hughes, K Jeppson, P Larsson-Edefors, M Sheeran, P Stenstrom, ...
Proceedings of the IEEE NorChip conference, 52-55, 2003
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