Djones Lettnin
Djones Lettnin
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Zitiert von
Zitiert von
A survey on formal verification techniques for safety-critical systems-on-chip
T Grimm, D Lettnin, M Hübner
Electronics 7 (6), 81, 2018
Electrocardiogram pattern recognition by means of MLP network and PCA: A case study on equal amount of input signal types
F Vargas, D Lettnin, MCF de Castro, M Macarthy
VII Brazilian Symposium on Neural Networks, 2002. SBRN 2002. Proceedings …, 2002
Implantes cocleares: aspectos tecnológicos e papel socioeconômico
D Tefili, GFG Barrault, AA Ferreira, JA Cordioli, DV Lettnin
Revista Brasileira de Engenharia Biomédica 29, 414-433, 2013
Verification of temporal properties in automotive embedded software
D Lettnin, PK Nalla, J Ruf, T Kropf, W Rosenstiel, T Kirsten, ...
Proceedings of the conference on Design, automation and test in Europe, 164-169, 2008
Synthesizable VHDL design for FPGAs
EA Bezerra, DV Lettnin
Springer International Publishing, 2014
Semiformal verification of temporal properties in automotive hardware dependent software
D Lettnin, PK Nalla, J Behrend, J Ruf, J Gerlach, T Kropf, W Rosenstiel, ...
2009 Design, Automation & Test in Europe Conference & Exhibition, 1214-1217, 2009
Synthesis of embedded SystemC design: A case study of digital neural networks
D Lettnin, A Braun, M Bodgan, J Gerlach, W Rosenstiel
Proceedings Design, Automation and Test in Europe Conference and Exhibition …, 2004
Non-intrusive fault tolerance in soft processors through circuit duplication
F Ferlini, FA da Silva, EA Bezerra, DV Lettnin
2012 13th Latin American Test Workshop (LATW), 1-6, 2012
Coverage driven verification applied to embedded software
D Lettnin, M Winterholer, A Braun, J Gerlach, J Ruf, T Kropf, W Rosenstiel
IEEE Computer Society Annual Symposium on VLSI (ISVLSI'07), 159-164, 2007
Embedded software verification and debugging
D Lettnin, M Winterholer
Springer, 2017
Automatic property generation for formal verification applied to hdl-based design of an on-board computer for space applications
W Silva, E Bezerra, M Winterholer, D Lettnin
2013 14th Latin American Test Workshop-LATW, 1-6, 2013
Scalable hybrid verification for embedded software
J Behrend, D Lettnin, P Heckeler, J Ruf, T Kropf, W Rosenstiel
2011 Design, Automation & Test in Europe, 1-6, 2011
Simulation-based verification of the MOST netinterface specification revision 3.0
A Braun, O Bringmann, D Lettnin, W Rosenstiel
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010
Scalable and optimized hybrid verification of embedded software
J Behrend, D Lettnin, A Grünhage, J Ruf, T Kropf, W Rosenstiel
Journal of Electronic Testing 31, 151-166, 2015
On the mitigation of conducted electromagnetic immunity by means of SW-based fault handling mechanisms
FL Vargas, D Brum, DP Prestes, LM VEIRAS BOLZANI
Titolo volume non avvalorato, 2003
An adaptive closed-loop verification approach in UVM-systemC for AMS circuits
JS Barros, VH Schulz, DV Lettnin
2018 31st Symposium on Integrated Circuits and Systems Design (SBCCI), 1-6, 2018
Extending universal verification methodology with fault injection capabilities
D Lohmann, F Maziero, EJ dos Santos, D Lettnin
2018 IEEE 9th Latin American Symposium on Circuits & Systems (LASCAS), 1-4, 2018
A complete CubeSat mission: the Floripa-Sat experience
PRC Villa, L Slongo, J Salamanca, V Martins, F Silva, SV Martinez, ...
1st IAA Latin American Cubesat Workshop 2, 307-314, 2014
Synthesizable VHDL Design for FPGAs, 2014
E Bezerra, D Lettnin
Springer. Disponível na biblioteca. FACULDADE DE INFORMÁTICA Centro …, 0
The experience of designing and developing the on-board electronics of a Cubesat in Brazil
V Martins, P Villa, L Slongo, J Salamanca, F Sabino, S Martinez, L Mariga, ...
1st IAA Latin American CubeSat Workshop 2 (3), 69-73, 2016
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