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Huawei Li
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DeepBurning: automatic generation of FPGA-based learning accelerators for the neural network family
Y Wang, J Xu, Y Han, H Li, X Li
Proceedings of the 53rd Annual Design Automation Conference, 110, 2016
2542016
Engn: A high-throughput and energy-efficient accelerator for large graph neural networks
S Liang, Y Wang, C Liu, L He, LI Huawei, D Xu, X Li
IEEE Transactions on Computers 70 (9), 1511-1525, 2020
1542020
An abacus turn model for time/space-efficient reconfigurable routing
B Fu, Y Han, J Ma, H Li, X Li
Proceeding of the 38th annual international symposium on Computer …, 2011
1212011
On topology reconfiguration for defect-tolerant NoC-based homogeneous manycore systems
L Zhang, Y Han, Q Xu, X Li, H Li
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 17 (9 …, 2009
912009
Zonedefense: A fault-tolerant routing for 2-d meshes without virtual channels
B Fu, Y Han, H Li, X Li
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (1), 113-126, 2014
572014
SoftPCM: Enhancing energy efficiency and lifetime of phase change memory in video applications via approximate write
Y Fang, H Li, X Li
2012 IEEE 21st Asian Test Symposium, 131-136, 2012
522012
Cognitive {SSD}: A Deep Learning Engine for In-Storage Data Retrieval
S Liang, Y Wang, Y Lu, Z Yang, H Li, X Li
2019 {USENIX} Annual Technical Conference ({USENIX}{ATC} 19), 395-410, 2019
502019
Automatic Test Program Generation Using Executing-Trace-Based Constraint Extraction for Embedded Processors
Y Zhang, H Li, X Li
IEEE Transactions on Very Large Scale Integration Systems 21 (7), 1220-1233, 2013
442013
nGFSIM: A GPU-Based Fault Simulator for 1-to-n Detection and its Applications
H Li, D Xu, Y Han, KT Cheng, X Li
Test Conference (ITC), 2010 IEEE International, 1-10, 2010
422010
An on-chip clock generation scheme for faster-than-at-speed delay testing
S Pei, H Li, X Li
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010
382010
Fault Tolerance Mechanism in Chip Many-Core Processors*
L Zhang, Y Han, H Li, X Li
Tsinghua Science & Technology 12, 169-174, 2007
382007
Robust test generation for precise crosstalk-induced path delay faults
H Li, P Shen, X Li
VLSI Test Symposium, 2006. Proceedings. 24th IEEE, 6 pp.-305, 2006
382006
FCN-engine: accelerating deconvolutional layers in classic CNN processors
D Xu, K Tu, Y Wang, C Liu, B He, H Li
Proceedings of the International Conference on Computer-Aided Design, 22, 2018
362018
Real-time meets approximate computing: An elastic CNN inference accelerator with adaptive trade-off between QoS and QoR
Y Wang, H Li, X Li
Proceedings of the 54th Annual Design Automation Conference 2017, 33, 2017
362017
Retraining-based timing error mitigation for hardware neural networks
J Deng, Y Fang, Z Du, Y Wang, H Li, O Temam, P Ienne, D Novo, X Li, ...
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 593-596, 2015
362015
A fault criticality evaluation framework of digital systems for error tolerant video applications
Y Fang, H Li, X Li
2011 Asian Test Symposium, 329-334, 2011
362011
Test resource partitioning based on efficient response compaction for test time and tester channels reduction
YH Han, XW Li, HW Li, A Chandra
Journal of Computer Science and Technology 20 (2), 201-209, 2005
362005
Economizing TSV resources in 3-D network-on-chip design
Y Wang, YH Han, L Zhang, BZ Fu, C Liu, HW Li, X Li
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (3), 493-506, 2015
342015
Re-architecting the on-chip memory sub-system of machine-learning accelerator for embedded devices
Y Wang, H Li, X Li
Computer-Aided Design (ICCAD), 2016 IEEE/ACM International Conference on, 1-6, 2016
332016
Embedded test decompressor to reduce the required channels and vector memory of tester for complex processor circuit
Y Han, Y Hu, X Li, H Li, A Chandra
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 15 (5), 531-540, 2007
322007
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