Follow
Luke Everson
Title
Cited by
Cited by
Year
CorNET: Deep learning framework for PPG-based heart rate estimation and biometric identification in ambulant environment
D Biswas, L Everson, M Liu, M Panwar, BE Verhoef, S Patki, CH Kim, ...
IEEE transactions on biomedical circuits and systems 13 (2), 282-291, 2019
2922019
BiometricNet: Deep Learning based Biometric Identification using Wrist-Worn PPG
L Everson, D Biswas, M Panwar, D Rodopoulos, A Acharyya, CH Kim, ...
2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018
742018
A scalable time-based integrate-and-fire neuromorphic core with brain-inspired leak and local lateral inhibition capabilities
M Liu, LR Everson, CH Kim
2017 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2017
462017
An Energy-Efficient One-Shot Time-Based Neural Network Accelerator Employing Dynamic Threshold Error Correction in 65 nm
LR Everson, M Liu, N Pande, CH Kim
IEEE Journal of Solid-State Circuits 54 (10), 2777-2785, 2019
342019
An Embedded nand Flash-Based Compute-In-Memory Array Demonstrated in a Standard Logic Process
M Kim, M Liu, LR Everson, CH Kim
IEEE Journal of Solid-State Circuits 57 (2), 625-638, 2021
312021
A 68 Parallel Row Access Neuromorphic Core with 22K Multi-Level Synapses Based on Logic-Compatible Embedded Flash Memory Technology
M Kim, J Kim, G Park, L Everson, H Kim, S Song, S Lee, CH Kim
2018 IEEE International Electron Devices Meeting (IEDM), 15.4. 1-15.4. 4, 2018
282018
A 3D NAND Flash Ready 8-Bit Convolutional Neural Network Core Demonstrated in a Standard Logic Process
M Kim, M Liu, L Everson, G Park, Y Jeon, S Kim, S Lee, S Song, CH Kim
2019 IEEE International Electron Devices Meeting (IEDM), 38.3. 1-38.3. 4, 2019
212019
A Physical Unclonable Function based on Capacitor Mismatch in a Charge-Redistribution SAR-ADC
Q Tang, WH Choi, L Everson, KK Parhi, CH Kim
2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018
152018
A 104.8 TOPS/W One-Shot Time-Based Neuromorphic Chip Employing Dynamic Threshold Error Correction in 65nm
LR Everson, M Liu, N Pande, CH Kim
2018 IEEE Asian Solid-State Circuits Conference (A-SSCC), 273-276, 2018
142018
Analysis of Neutron-Induced Multibit-Upset Clusters in a 14-nm Flip-Flop Array
S Kumar, M Cho, L Everson, Q Tang, P Meinerzhagen, A Malavasi, ...
IEEE Transactions on Nuclear Science 66 (6), 918-925, 2019
132019
Understanding the Key Parameter Dependences Influencing the Soft-Error Susceptibility of Standard Combinational Logic
N Pande, S Kumar, LR Everson, CH Kim
IEEE Transactions on Nuclear Science 67 (1), 116-125, 2019
112019
2.5 A 40× 40 Four-Neighbor Time-Based In-Memory Computing Graph ASIC Chip Featuring Wavefront Expansion and 2D Gradient Control
LR Everson, SS Sapatnekar, CH Kim
2019 IEEE International Solid-State Circuits Conference-(ISSCC), 50-52, 2019
11*2019
BioTranslator: Inferring R-Peaks from Ambulatory Wrist-Worn PPG Signal
L Everson, D Biswas, BE Verhoef, CH Kim, C Van Hoof, M Konijnenburg, ...
2019 41st Annual International Conference of the IEEE Engineering in …, 2019
102019
Statistical characterization of radiation-induced pulse waveforms and flip-flop soft errors in 14nm tri-gate CMOS using a back-sampling chain (BSC) technique
S Kumar, M Cho, L Everson, H Kim, Q Tang, P Mazanec, P Meinerzhagen, ...
VLSI Technology, 2017 Symposium on, C114-C115, 2017
72017
A Time-Based Intra-Memory Computing Graph Processor Featuring A* Wavefront Expansion and 2-D Gradient Control
LR Everson, SS Sapatnekar, CH Kim
IEEE Journal of Solid-State Circuits 56 (7), 2281-2290, 2021
62021
An Ultra-Dense Irradiation Test Structure with a NAND/NOR Readout Chain for Characterizing Soft Error Rates of 14nm Combinational Logic Circuits
S Kumar, M Cho, L Everson, H Kim, Q Tang, P Mazanec, P Meinerzhagen, ...
6*
METHOD OF GENERATING A MODEL FOR HEART RATE ESTIMATION FROM A PHOTOPLETHYSMOGRAPHY SIGNAL AND A METHOD AND A DEVICE FOR HEART RATE ESTIMATION
D Biswas, L Everson, M Konijnenburg, C Van Hoof, N Van Helleputte
US Patent App. 16/576,759, 2020
52020
Neutron-Induced Pulsewidth Distribution of Logic Gates Characterized Using a Pulse Shrinking Chain-Based Test Structure
N Pande, S Kumar, LR Everson, G Park, I Ahmed, CH Kim
IEEE Transactions on Nuclear Science 68 (12), 2736-2747, 2021
32021
Design space exploration for efficient computing in Solid State drives with the Storage Processing Unit
M Minglani, A Nagarajan, S Deshapande, L Everson, DJ Lilja
2015 IEEE International Conference on Networking, Architecture and Storage …, 2015
32015
A 0.0094mm2/Channel Time-Based Beat Frequency ADC in 65nm CMOS for Intra-Electrode Neural Recording
L Everson, S Kundu, G Chen, Z Yang, TJ Ebner, CH Kim
2018 IEEE Biomedical Circuits and Systems Conference (BioCAS), 1-4, 2018
22018
The system can't perform the operation now. Try again later.
Articles 1–20