| Process technology variation KJ Kuhn, MD Giles, D Becher, P Kolar, A Kornfeld, R Kotlyar, ST Ma, ... IEEE Transactions on Electron Devices 58 (8), 2197-2208, 2011 | 471 | 2011 |
| A 32nm SoC platform technology with 2nd generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product … CH Jan, M Agostinelli, M Buehler, ZP Chen, SJ Choi, G Curello, ... 2009 IEEE International Electron Devices Meeting (IEDM), 1-4, 2009 | 345 | 2009 |
| Method and apparatus for non-contact electrostatic actuation of droplets P Kolar, RB Fair US Patent 6,989,234, 2006 | 211 | 2006 |
| Erratic fluctuations of SRAM cache Vmin at the 90nm process technology node M Agostinelli, J Hicks, J Xu, B Woolery, K Mistry, K Zhang, S Jacobs, ... IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest …, 2005 | 149 | 2005 |
| A 1.1 GHz 12 A/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications Y Wang, HJ Ahn, U Bhattacharya, Z Chen, T Coan, F Hamzaoglu, ... IEEE Journal of Solid-State Circuits 43 (1), 172-179, 2008 | 140 | 2008 |
| IEEE International Electron Devices Meeting (IEDM) CH Jan, M Agostinelli, M Buehler, ZP Chen, SJ Choi, G Curello, ... San Francisco, USA, 3.1, 2012 | 91 | 2012 |
| A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management Y Wang, U Bhattacharya, F Hamzaoglu, P Kolar, Y Ng, L Wei, Y Zhang, ... 2009 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2009 | 79 | 2009 |
| A 32nm High-k metal gate SRAM with adaptive dynamic stability enhancement for low-voltage operation H Nho, P Kolar, F Hamzaoglu, Y Wang, E Karl, YG Ng, U Bhattacharya, ... 2010 IEEE International Solid-State Circuits Conference-(ISSCC), 346-347, 2010 | 62 | 2010 |
| A 4.0 GHz 291 Mb voltage-scalable SRAM design in a 32 nm high-k+ metal-gate CMOS technology with integrated power management Y Wang, U Bhattacharya, F Hamzaoglu, P Kolar, YG Ng, L Wei, Y Zhang, ... IEEE Journal of Solid-State Circuits 45 (1), 103-110, 2009 | 59 | 2009 |
| IEDM Tech. Dig. CH Jan, M Agostinelli, M Buehler, ZP Chen, SJ Choi, G Curello, ... IEDM Tech. Dig, 44-47, 2012 | 41 | 2012 |
| Dual-port static random access memory (SRAM) P Kolar, GH Pandya, U Bhattacharya, Z Guo US Patent 9,208,853, 2015 | 37 | 2015 |
| A 32 nm high-k metal gate SRAM with adaptive dynamic stability enhancement for low-voltage operation P Kolar, E Karl, U Bhattacharya, F Hamzaoglu, H Nho, YG Ng, Y Wang, ... IEEE journal of solid-state circuits 46 (1), 76-84, 2010 | 36 | 2010 |
| Negative bitline write assist circuit and method for operating the same P Kolar, J Riley, G Pandya US Patent 9,378,788, 2016 | 32 | 2016 |
| Bit cell optimizations and circuit techniques for nanoscale SRAM design F Hamzaoglu, Y Wang, P Kolar, L Wei, YG Ng, U Bhattacharya, K Zhang IEEE Design & Test of Computers 28 (1), 22-31, 2011 | 20 | 2011 |
| Adaptive and dynamic stability enhancement for memories P Kolar, F Hamzaoglu, Y Wang, EA Karl, YG Ng, U Bhattacharya, ... US Patent 8,451,670, 2013 | 14 | 2013 |
| Low-power, p-channel enhancement-type metal-oxide semiconductor field-effect transistor (PMOSFET) SRAM cells P Kolar, HZ Massoud US Patent 7,286,389, 2007 | 4 | 2007 |
| Capacitive wordline boosting JP Kulkarni, P Kolar, A Sharma, S Chatterjee, K Subramanian, F Sheikh, ... US Patent 10,002,654, 2018 | 3 | 2018 |
| Sub-550mV SRAM design in 22nm FinFET low power (22FFL) technology with self-induced collapse write assist D Kim, J Wiedemer, P Kolar, A Shrivastava, J Shah, S Nalam, G Baek, ... 2018 IEEE Symposium on VLSI Technology, 151-152, 2018 | 3 | 2018 |
| Dual-port static random access memory (SRAM) P Kolar, GH Pandya, U Bhattacharya, Z Guo US Patent 9,607,687, 2017 | 1 | 2017 |
| Computer memory arrays employing memory banks and integrated serializer/de-serializer circuits for supporting serialization/de-serialization of read/write data in burst read … P Kolar, SE Liles US Patent App. 17/847,875, 2023 | | 2023 |
