| Parameterized posit arithmetic hardware generator R Chaurasiya, J Gustafson, R Shrestha, J Neudorfer, S Nambiar, K Niyogi, ... 2018 IEEE 36th International Conference on Computer Design (ICCD), 334-341, 2018 | 79 | 2018 |
| High-Throughput Turbo Decoder With Parallel Architecture for LTE Wireless Communication Standards R Shrestha, RP Paily IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS — I: REGULAR PAPERS 61 (9), 2699-2710, 2014 | 59 | 2014 |
| High-Throughput LDPC-Decoder Architecture Using Efficient Comparison Techniques & Dynamic Multi-Frame Processing Schedule S Kumawat, R Shrestha, N Daga, R Paily IEEE TRANSACTIONS ON CIRCUITS & SYSTEMS I: REGULAR PAPERS 62 (5), 1421-1430, 2015 | 49 | 2015 |
| Hardware-Efficient and Fast Sensing-Time Maximum-Minimum-Eigenvalue-Based Spectrum Sensor for Cognitive Radio Network RB Chaurasiya, R Shrestha IEEE TRANSACTIONS ON CIRCUITS & SYSTEMS I: REGULAR PAPERS 66 (11), 4448-4461, 2019 | 27 | 2019 |
| Reconfigurable & Memory-Efficient Cyclostationary Spectrum Sensor for Cognitive-Radio Wireless Networks MS Murty, R Shrestha IEEE TRANSACTIONS ON CIRCUITS & SYSTEMS II: EXPRESS BRIEFS 65 (8), 1039-1043, 2018 | 23 | 2018 |
| Fast Sensing-Time and Hardware-Efficient Eigenvalue-Based Blind Spectrum Sensors for Cognitive Radio Network RB Chaurasiya, R Shrestha IEEE TRANSACTIONS ON CIRCUITS & SYSTEMS I: REGULAR PAPERS 67 (4), 1296-1309, 2020 | 19 | 2020 |
| VLSI Architecture for Cyclostationary Feature Detection Based Spectrum Sensing for Cognitive-Radio Wireless Networks and Its ASIC Implementation MS Murty, R Shrestha IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016, 69-74, 2016 | 16 | 2016 |
| Multi‐standard high‐throughput and low‐power quasi‐cyclic low density parity check decoder for worldwide interoperability for microwave access and wireless fidelity standards VK Kanchetla, R Shrestha, R Paily IET Circuits, Devices & Systems 10 (2), 111-120, 2016 | 14 | 2016 |
| High-Speed and Hardware-Efficient Successive Cancellation Polar-Decoder R Shrestha, A Sahoo IEEE TRANSACTIONS ON CIRCUITS & SYSTEMS II: EXPRESS BRIEFS, 2018 | 13 | 2018 |
| Embedded hardware prototype for gas detection and monitoring system in Android mobile platform R Kurzekar, H Arora, R Shrestha 2017 IEEE International Symposium on Nanoelectronic and Information Systems …, 2017 | 13 | 2017 |
| Design and implementation of a high speed map decoder architecture for turbo decoding R Shrestha, R Paily 26th IEEE International Conference on VLSI Design (VLSID) and 12th …, 2013 | 12 | 2013 |
| Hardware implementation and VLSI design of spectrum sensor for next‐generation LTE‐A cognitive‐radio wireless network MS Murty, R Shrestha IET Circuits, Devices & Systems 12 (5), 542-550, 2018 | 11 | 2018 |
| PGMA: an algorithmic approach for multi-objective hardware software partitioning N Govil, R Shrestha, SR Chowdhury Microprocessors and Microsystems 54, 83-96, 2017 | 11 | 2017 |
| A new partially-parallel VLSI-architecture of quasi-cyclic LDPC decoder for 5G new-radio A Verma, R Shrestha 2020 33rd International Conference on VLSI Design and 2020 19th …, 2020 | 9 | 2020 |
| High-throughput and high-speed polar-decoder VLSI-architecture for 5G new radio R Shrestha, P Bansal, S Srinivasan 2019 32nd International Conference on VLSI Design and 2019 18th …, 2019 | 9 | 2019 |
| Hardware Implementation of Max-Log-MAP algorithm based on MacLaurin series for turbo decoder R Shrestha, R Paily 2011 International Conference on Communications and Signal Processing, 509-511, 2011 | 9 | 2011 |
| A new VLSI architecture of next-generation QC-LDPC decoder for 5G new-radio wireless-communication standard A Verma, R Shrestha 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020 | 8 | 2020 |
| Area-Efficient and Scalable Data-Fusion based Cooperative Spectrum Sensor for Cognitive Radio RB Chaurasiya, R Shrestha IEEE TRANSACTIONS ON CIRCUITS & SYSTEMS II: EXPRESS BRIEFS, 2020 | 8 | 2020 |
| Design and Implementation of Area-Efficient and Low-Power Configurable Booth-Multiplier R Shrestha, U Rastogi 2016 29th International Conference on VLSI Design and 2016 15th …, 2016 | 8 | 2016 |
| High-speed and low-power VLSI-architecture for inexact speculative adder R Shrestha 2017 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 1-4, 2017 | 7 | 2017 |
Roy PailyProfessor, Electronics and Electrical Engineering and Centre for Nanotechnology, IIT Guwahati確認したメール アドレス: iitg.ac.in
