Gilles Sassatelli
Gilles Sassatelli
LIRMM CNRS / University of Montpellier
Verified email at
Cited by
Cited by
Accuracy evaluation of gem5 simulator system
A Butko, R Garibotti, L Ost, G Sassatelli
7th International workshop on reconfigurable and communication-centric …, 2012
Tec-tree: A low-cost, parallelizable tree for efficient defense against memory replay attacks
R Elbaz, D Champagne, RB Lee, L Torres, G Sassatelli, P Guillemin
Cryptographic Hardware and Embedded Systems-CHES 2007: 9th International …, 2007
A parallelized way to provide data encryption and integrity checking on a processor-memory bus
R Elbaz, L Torres, G Sassatelli, P Guillemin, M Bardouillet, A Martinez
Proceedings of the 43rd annual Design Automation Conference, 506-509, 2006
Heterogeneous vs homogeneous MPSoC approaches for a mobile LTE modem
C Jalier, D Lattard, AA Jerraya, G Sassatelli, P Benoit, L Torres
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010
Non-volatile processor based on MRAM for ultra-low-power IoT devices
S Senni, L Torres, G Sassatelli, A Gamatie
ACM Journal on Emerging Technologies in Computing Systems (JETC) 13 (2), 1-23, 2016
An adaptive message passing mpsoc framework
G Marchesan Almeida, G Sassatelli, P Benoit, N Saint-Jean, S Varyani, ...
International Journal of Reconfigurable Computing 2009, 2009
Hardware engines for bus encryption: a survey of existing techniques
R Elbaz, L Torres, G Sassatelli, P Guillemin, C Anguille, C Buatois, ...
Design, Automation and Test in Europe, 40-45, 2005
Temperature-aware distributed run-time optimization on MP-SoC using game theory
D Puschini, F Clermidy, P Benoit, G Sassatelli, L Torres
2008 IEEE Computer Society Annual Symposium on VLSI, 375-380, 2008
Full-system simulation of big. little multicore architecture for performance and energy exploration
A Butko, F Bruguier, A Gamatié, G Sassatelli, D Novo, L Torres, M Robert
2016 ieee 10th international symposium on embedded multicore/many-core …, 2016
A non-volatile run-time FPGA using thermally assisted switching MRAMS
Y Guillemenet, L Torres, G Sassatelli, N Bruchon, I Hassoune
2008 International Conference on Field Programmable Logic and Applications …, 2008
Power-aware dynamic mapping heuristics for NoC-based MPSoCs using a unified model-based approach
L Ost, M Mandelli, GM Almeida, L Moller, LS Indrusiak, G Sassatelli, ...
ACM Transactions on Embedded Computing Systems (TECS) 12 (3), 1-22, 2013
New nonvolatile FPGA concept using magnetic tunneling junction
N Bruchon, L Torres, G Sassatelli, G Cambon
IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and …, 2006
Exploring MRAM technologies for energy efficient systems-on-chip
S Senni, L Torres, G Sassatelli, A Gamatie, B Mussard
IEEE Journal on emerging and selected topics in circuits and systems 6 (3 …, 2016
Evaluating the impact of task migration in multi-processor systems-on-chip
GM Almeida, S Varyani, R Busseuil, G Sassatelli, P Benoit, L Torres, ...
Proceedings of the 23rd symposium on Integrated circuits and system design …, 2010
A trace-driven approach for fast and accurate simulation of manycore architectures
A Butko, R Garibotti, L Ost, V Lapotre, A Gamatie, G Sassatelli, ...
The 20th Asia and South Pacific Design Automation Conference, 707-712, 2015
Trends on the application of emerging nonvolatile memory to processors and programmable devices
L Torres, RM Brum, LV Cargnini, G Sassatelli
2013 IEEE International Symposium on Circuits and Systems (ISCAS), 101-104, 2013
Non-volatile run-time field-programmable gate arrays structures using thermally assisted switching magnetic random access memories
Y Guillemenet, L Torres, G Sassatelli
IET Computers & Digital Techniques 4 (3), 211-226, 2010
Highly scalable dynamically reconfigurable systolic ring-architecture for DSP applications
G Sassatelli, L Torres, P Benoit, T Gil, C Diou, G Cambon, J Galy
Proceedings 2002 Design, Automation and Test in Europe Conference and …, 2002
An introduction to multi-core system on chip–trends and challenges
L Torres, P Benoit, G Sassatelli, M Robert, F Clermidy, D Puschini
Multiprocessor system-on-chip: hardware design and tool integration, 1-21, 2010
Hs-scale: a hardware-software scalable mp-soc architecture for embedded systems
N Saint-Jean, G Sassatelli, P Benoit, L Torres, M Robert
IEEE Computer Society Annual Symposium on VLSI (ISVLSI'07), 21-28, 2007
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