| Numerical function generators using LUT cascades T Sasao, S Nagayama, JT Butler IEEE Transactions on Computers 56 (6), 826-838, 2007 | 92 | 2007 |
| On the optimization of heterogeneous MDDs S Nagayama, T Sasao IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2005 | 58 | 2005 |
| Compact representations of logic functions using heterogeneous MDDs S Nagayama, T Sasao IEICE transactions on fundamentals of electronics, communications and …, 2003 | 58 | 2003 |
| Minimization of average path length in BDDs by variable reordering S Nagayama, A Mishchenko, T Sasao, JT Butler International Workshop on Logic and Synthesis, 207-213, 2003 | 34 | 2003 |
| Programmable numerical function generators based on quadratic approximation: architecture and synthesis method S Nagayama, T Sasao, JT Butler Proceedings of the 2006 Asia and South Pacific Design Automation Conference …, 2006 | 27 | 2006 |
| On the minimization of longest path length for decision diagrams S Nagayama, T Sasao IWLS04, 28-35, 2004 | 26 | 2004 |
| Complexities of graph-based representations for elementary functions S Nagayama, T Sasao IEEE Transactions on Computers 58 (1), 106-119, 2008 | 23 | 2008 |
| Representations of elementary functions using edge-valued MDDs S Nagayama, T Sasao 37th International Symposium on Multiple-Valued Logic (ISMVL'07), 5-5, 2007 | 23 | 2007 |
| Code generation for embedded systems using heterogeneous MDDs S Nagayama, T Sasao the 12th workshop on Synthesis and System Integration of Mixed Information …, 2003 | 21 | 2003 |
| Compact numerical function generators based on quadratic approximation: Architecture and synthesis method S Nagayama, T Sasao, JT Butler IEICE transactions on fundamentals of electronics, communications and …, 2006 | 20 | 2006 |
| Analysis of multi-state systems with multi-state components using EVMDDs S Nagayama, T Sasao, JT Butler 2012 IEEE 42nd International Symposium on Multiple-Valued Logic, 122-127, 2012 | 18 | 2012 |
| Representations of elementary functions using binary moment diagrams T Sasao, S Nagayama 36th International Symposium on Multiple-Valued Logic (ISMVL'06), 28-28, 2006 | 18 | 2006 |
| A systolic regular expression pattern matching engine and its application to network intrusion detection Y Kawanaka, S Wakabayashi, S Nagayama 2008 International Conference on Field-Programmable Technology, 297-300, 2008 | 17 | 2008 |
| An efficient hardware matching engine for regular expression with nested Kleene operators Y Wakaba, M Inagi, S Wakabayashi, S Nagayama 2011 21st International Conference on Field Programmable Logic and …, 2011 | 16 | 2011 |
| An efficient heuristic for linear decomposition of index generation functions S Nagayama, T Sasao, JT Butler 2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL), 96-101, 2016 | 15 | 2016 |
| A GPGPU implementation of approximate string matching with regular expression operators and comparison with its FPGA implementation Y Utan, M Inagi, S Wakabayashi, S Nagayama Proceedings of the International Conference on Parallel and Distributed …, 2012 | 15 | 2012 |
| Programmable numerical function generators: architectures and synthesis method T Sasao, S Nagayama, JT Butler International Conference on Field Programmable Logic and Applications, 2005 …, 2005 | 15 | 2005 |
| Representations of logic functions using QRMDDs S Nagayama, T Sasao, Y Iguchi, M Matsuura Proceedings 32nd IEEE International Symposium on Multiple-Valued Logic, 261-267, 2002 | 15 | 2002 |
| Efficient FPGA-based hardware algorithms for approximate string matching S Mikami, Y Kawanaka, S Wakabayashi, S Nagayama IEICE Proceedings Series 39 (D2-1), 2008 | 14 | 2008 |
| A systematic design method for two-variable numeric function generators using multiple-valued decision diagrams S Nagayama, T Sasao, JT Butler IEICE TRANSACTIONS on Information and Systems 93 (8), 2059-2067, 2010 | 13 | 2010 |
Tsutomu SasaoVisiting Professor, Meiji UniversityBestätigte E-Mail-Adresse bei cs.meiji.ac.jp
