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Praveen Raghavan
Praveen Raghavan
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Device exploration of nanosheet transistors for sub-7-nm technology node
D Jang, D Yakimets, G Eneman, P Schuddinck, MG Bardon, P Raghavan, ...
IEEE Transactions on Electron Devices 64 (6), 2707-2713, 2017
2212017
Vertical GAAFETs for the ultimate CMOS scaling
D Yakimets, G Eneman, P Schuddinck, TH Bao, MG Bardon, P Raghavan, ...
IEEE Transactions on Electron Devices 62 (5), 1433-1439, 2015
2022015
Coarse-grained reconfigurable array architectures
BD Sutter, P Raghavan, A Lambrechts
Handbook of signal processing systems, 427-472, 2019
1362019
Understanding energy efficiency benefits of carbon nanotube field-effect transistors for digital VLSI
G Hills, MG Bardon, G Doornbos, D Yakimets, P Schuddinck, R Baert, ...
IEEE Transactions on Nanotechnology 17 (6), 1259-1269, 2018
1192018
Impact of Wire Geometry on Interconnect RC and Circuit Delay
I Ciofi, A Contino, PJ Roussel, R Baert, VH Vega-Gonzalez, K Croes, ...
IEEE Transactions on Electron Devices 63 (6), 2488-2496, 2016
1012016
Power aware FinFET and lateral nanosheet FET targeting for 3nm CMOS technology
D Yakimets, MG Bardon, D Jang, P Schuddinck, Y Sherazi, P Weckx, ...
2017 IEEE International Electron Devices Meeting (IEDM), 20.4. 1-20.4. 4, 2017
982017
Self-heating on bulk FinFET from 14nm down to 7nm node
D Jang, E Bury, R Ritzenthaler, MG Bardon, T Chiarella, K Miyaguchi, ...
2015 IEEE International Electron Devices Meeting (IEDM), 11.6. 1-11.6. 4, 2015
952015
Polarity control in WSe2 double-gate transistors
GV Resta, S Sutar, Y Balaji, D Lin, P Raghavan, I Radu, F Catthoor, ...
Scientific reports 6 (1), 29448, 2016
912016
Future software-defined radio platforms and mapping flows
M Palkovic, P Raghavan, M Li, A Dejonghe, L Van der Perre, F Catthoor
IEEE Signal Processing Magazine 27 (2), 22-33, 2010
812010
Extreme scaling enabled by 5 tracks cells: Holistic design-device co-optimization for FinFETs and lateral nanowires
MG Bardon, Y Sherazi, P Schuddinck, D Jang, D Yakimets, P Debacker, ...
2016 IEEE International Electron Devices Meeting (IEDM), 28.2. 1-28.2. 4, 2016
752016
Comparison of reaction-diffusion and atomistic trap-based BTI models for logic gates
H Kükner, S Khan, P Weckx, P Raghavan, S Hamdioui, B Kaczer, ...
IEEE transactions on device and materials reliability 14 (1), 182-193, 2013
722013
Defect-based methodology for workload-dependent circuit lifetime projections-Application to SRAM
P Weckx, B Kaczer, M Toledano-Luque, T Grasser, PJ Roussel, H Kukner, ...
2013 IEEE International Reliability Physics Symposium (IRPS), 3A. 4.1-3A. 4.7, 2013
672013
Design and benchmarking of hybrid CMOS-spin wave device circuits compared to 10nm CMOS
O Zografos, B Sorée, A Vaysset, S Cosemans, L Amaru, PE Gaillardon, ...
2015 IEEE 15th International Conference on Nanotechnology (IEEE-NANO), 686-689, 2015
612015
Bias temperature instability analysis of FinFET based SRAM cells
S Khan, I Agbo, S Hamdioui, H Kukner, B Kaczer, P Raghavan, F Catthoor
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014
612014
Power breakdown analysis for a heterogeneous NoC platform running a video application
A Lambrechts, P Raghavan, A Leroy, G Talavera, TV Aa, M Jayapala, ...
2005 IEEE International Conference on Application-Specific Systems …, 2005
602005
A unified instruction set programmable architecture for multi-standard advanced forward error correction
F Naessens, B Bougard, S Bressinck, L Hollevoet, P Raghavan, ...
2008 IEEE Workshop on Signal Processing Systems, 31-36, 2008
582008
Vertical device architecture for 5nm and beyond: device & circuit implications
AVY Thean, D Yakimets, TH Bao, P Schuddinck, S Sakhare, MG Bardon, ...
2015 Symposium on VLSI Technology (VLSI Technology), T26-T27, 2015
562015
BTI impact on logical gates in nano-scale CMOS technology
S Khan, S Hamdioui, H Kukner, P Raghavan, F Catthoor
2012 IEEE 15th International Symposium on Design and Diagnostics of …, 2012
562012
The impact of sequential-3D integration on semiconductor scaling roadmap
A Mallik, A Vandooren, L Witters, A Walke, J Franco, Y Sherazi, P Weckx, ...
2017 IEEE International Electron Devices Meeting (IEDM), 32.1. 1-31.1. 4, 2017
552017
A 200Mbps+ 2.14 nJ/b digital baseband multi processor system-on-chip for SDRs
V Derudder, B Bougard, A Couvreur, A Dewilde, S Dupont, L Folens, ...
2009 Symposium on VLSI Circuits, 292-293, 2009
542009
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