Alireza Mahzoon
Alireza Mahzoon
Bestätigte E-Mail-Adresse bei informatik.uni-bremen.de - Startseite
Titel
Zitiert von
Zitiert von
Jahr
RevSCA: Using reverse engineering to bring light into backward rewriting for big and dirty multipliers
A Mahzoon, D Große, R Drechsler
Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019
212019
PolyCleaner: clean your polynomials before backward rewriting to verify million-gate multipliers
A Mahzoon, D Große, R Drechsler
Proceedings of the International Conference on Computer-Aided Design, 1-8, 2018
212018
Towards formal verification of optimized and industrial multipliers
A Mahzoon, D Große, C Scholl, R Drechsler
2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 544-549, 2020
92020
Combining symbolic computer algebra and boolean satisfiability for automatic debugging and fixing of complex multipliers
A Mahzoon, D Große, R Drechsler
2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 351-356, 2018
92018
OptiFEX: A framework for exploring area-efficient floating point expressions on FPGAs with optimized exponent/mantissa widths
A Mahzoon, B Alizadeh
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (1), 198-209, 2016
62016
Multi-objective optimization of floating point arithmetic expressions using iterative factorization
A Mahzoon, B Alizadeh
2015 IEEE Computer Society Annual Symposium on VLSI, 243-248, 2015
52015
ASCHyRO: Automatic Fault Localization of SystemC HLS Designs Using a Hybrid Accurate Rank Ordering Technique
M Goli, A Mahzoon, R Drechsler
2020 IEEE 38th International Conference on Computer Design (ICCD), 179-186, 2020
22020
GenMul: Generating architecturally complex multipliers to challenge formal verification tools
A Mahzoon, D Große, R Drechsler
Recent Findings in Boolean Techniques: Selected Papers from the 14th …, 2019
22019
Systematic Design Space Exploration of Floating-Point Expressions on FPGA
A Mahzoon, B Alizadeh
IEEE Transactions on Circuits and Systems II: Express Briefs 64 (3), 274-278, 2016
12016
REVSCA-2.0: SCA-based Formal Verification of Non-trivial Multipliers using Reverse Engineering and Local Vanishing Removal
A Mahzoon, D Große, R Drechsler
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2021
2021
Verifying Dividers Using Symbolic Computer Algebra and Don't Care Optimization
C Scholl, A Konrad, A Mahzoon, D Große, R Drechsler
2021 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2021
2021
Automated Debugging-Aware Visualization Technique for SystemC HLS Designs
M Goli, A Mahzoon, R Drechsler
Polynomial Formal Verification of Area-efficient and Fast Adders
A Mahzoon, R Drechsler
Late Breaking Results: Polynomial Formal Verification of Fast Adders
A Mahzoon, R Drechsler
complexity [MUX] 100, 2l, 0
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