| A Tunnel FET forScaling Below 0.6 V With a CMOS-Comparable Performance R Asra, M Shrivastava, KVRM Murali, RK Pandey, H Gossner, VR Rao IEEE Transactions on Electron Devices 58 (7), 1855-1863, 2011 | 187 | 2011 |
| Insights into the design and optimization of tunnel-FET devices and circuits A Pal, AB Sachid, H Gossner, VR Rao IEEE Transactions on Electron devices 58 (4), 1045-1053, 2011 | 133 | 2011 |
| Physical insight toward heat transport and an improved electrothermal modeling framework for FinFET architectures M Shrivastava, M Agrawal, S Mahajan, H Gossner, T Schulz, DK Sharma, ... IEEE Transactions on Electron Devices 59 (5), 1353-1363, 2012 | 108 | 2012 |
| Simulation methods for ESD protection development H Gossner, K Esmark, W Stadler Elsevier, 2003 | 89 | 2003 |
| A review on the ESD robustness of drain-extended MOS devices M Shrivastava, H Gossner IEEE Transactions on Device and Materials Reliability 12 (4), 615-625, 2012 | 87 | 2012 |
| Semiconductor devices H Gossner, R Rao, A Sachid, A Pal, R Asra US Patent 8,405,121, 2013 | 83 | 2013 |
| Tunnel-field-effect-transistor based gas-sensor: Introducing gas detection with a quantum-mechanical transducer D Sarkar, H Gossner, W Hansch, K Banerjee Applied Physics Letters 102 (2), 2013 | 75 | 2013 |
| Operating method for a semiconductor component K Esmark, H Gossner, P Riess, W Stadler, M Streibl, M Wendel US Patent 6,905,892, 2005 | 73 | 2005 |
| Electrostatic discharge protection element H Gossner, C Russ US Patent 7,919,816, 2011 | 69 | 2011 |
| Field effect transistor with a fin structure C Russ, H Gossner, T Schulz US Patent 7,646,046, 2010 | 68 | 2010 |
| ESD protection element and ESD protection device for use in an electrical circuit H Gossner, C Russ US Patent 8,455,949, 2013 | 62 | 2013 |
| Reliability aspects of gate oxide under ESD pulse stress A Ille, W Stadler, T Pompl, H Gossner, T Brodbeck, K Esmark, P Riess, ... 2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD …, 2007 | 62 | 2007 |
| Excitonic luminescence from locally grown SiGe wires and dots J Brunner, TS Rupp, H Gossner, R Ritter, I Eisele, G Abstreiter Applied physics letters 64 (8), 994-996, 1994 | 60 | 1994 |
| Vertical Si-metal-oxide-semiconductor field effect transistors with channel lengths of 50 nm by molecular beam epitaxy HGH Gossner, IEI Eisele, LRL Risch Japanese journal of applied physics 33 (4S), 2423, 1994 | 59 | 1994 |
| Part I: Mixed-signal performance of various high-voltage drain-extended MOS devices M Shrivastava, MS Baghini, H Gossner, VR Rao IEEE transactions on electron devices 57 (2), 448-457, 2009 | 58 | 2009 |
| Toward system on chip (SoC) development using FinFET technology: Challenges, solutions, process co-development & optimization guidelines M Shrivastava, R Mehta, S Gupta, N Agrawal, MS Baghini, DK Sharma, ... IEEE Transactions on Electron Devices 58 (6), 1597-1607, 2011 | 52 | 2011 |
| High voltage semiconductor devices M Shrivastava, MS Baghini, CC Russ, H Gossner, R Rao US Patent 8,664,720, 2014 | 50 | 2014 |
| Advanced 2D/3D ESD device simulation-a powerful tool already used in a pre-Si phase K Esmark, W Stadler, M Wendel, H Gossner, X Guggenmos, W Fichtner Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 …, 2000 | 49 | 2000 |
| Vertical MOS technology with sub-0.1 µm channel lengths H Gossner, F Wittmann, I Eisele, T Grabolla, D Behammer Electronics Letters 31 (16), 1394-1396, 1995 | 48 | 1995 |
| System level ESD co-design C Duvvury, H Gossner John Wiley & Sons, 2015 | 47 | 2015 |
