| Automated electrostatic discharge structure placement and routing in an integrated circuit YP Chen, STLNV Srujana, N Patel, RRL Reddy, S Subramanian, ... US Patent 7,657,858, 2010 | 6 | 2010 |
| System and method for optimizing slave transaction ID width based on sparse connection in multilayer multilevel interconnect system-on-chip architecture SK Pullagoundapatti, SR Kothamasu, VR Vallapaneni, C Pribbernow, ... US Patent 8,583,844, 2013 | 4 | 2013 |
| Ping-pong buffer using single-port memory VR Vallapaneni US Patent App. 14/231,417, 2015 | 2 | 2015 |
| Data dependent optimization of ROM structures VR Vallapaneni, A Prasad 2009 IEEE International Symposium on Circuits and Systems, 2749-2752, 2009 | 1 | 2009 |
| System and method for allocating transaction ID in a system with a plurality of processing modules VR Vallapaneni, SR Kothamasu, SK Pullagoundapatti US Patent 8,533,377, 2013 | | 2013 |
| Efficient techniques for noise characterization of sequential cells and macros VR Vallapeneni, RS Chevuri, B Xu, L Ye, K Chakraborty 19th International Conference on VLSI Design held jointly with 5th …, 2006 | | 2006 |
