James Tuck
James Tuck
Professor, Electrical and Computer Engineering, NC State University
Bestätigte E-Mail-Adresse bei ncsu.edu - Startseite
Zitiert von
Zitiert von
Bulk disambiguation of speculative threads in multiprocessors
L Ceze, J Tuck, J Torrellas, C Cascaval
ACM SIGARCH Computer Architecture News 34 (2), 227-238, 2006
SESC simulator, January 2005
J Renau, B Fraguela, J Tuck, W Liu, M Prvulovic, L Ceze, S Sarangi, ...
POSH: a TLS compiler that exploits program structure
W Liu, J Tuck, L Ceze, W Ahn, K Strauss, J Renau, J Torrellas
Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice …, 2006
BulkSC: Bulk enforcement of sequential consistency
L Ceze, J Tuck, P Montesinos, J Torrellas
Proceedings of the 34th annual international symposium on Computer …, 2007
Handling crosscutting constraints in domain-specific modeling
J Gray, T Bapty, S Neema, J Tuck
Communications of the ACM 44 (10), 87-93, 2001
Tasking with out-of-order spawn in TLS chip multiprocessors: Microarchitecture and compilation
J Renau, J Tuck, W Liu, L Ceze, K Strauss, J Torrellas
Proceedings of the 19th Annual International conference on Supercomputing …, 2005
Scalable cache miss handling for high memory-level parallelism
J Tuck, L Ceze, J Torrellas
2006 39th Annual IEEE/ACM International Symposium on Microarchitecture …, 2006
Proteus: A flexible and fast software supported hardware logging approach for nvm
S Shin, SK Tirukkovalluri, J Tuck, Y Solihin
Proceedings of the 50th Annual IEEE/ACM International Symposium on …, 2017
CAVA: Using checkpoint-assisted value prediction to hide L2 misses
L Ceze, K Strauss, J Tuck, J Torrellas, J Renau
ACM Transactions on Architecture and Code Optimization (TACO) 3 (2), 182-208, 2006
Thread-level speculation on a CMP can be energy efficient
J Renau, K Strauss, L Ceze, W Liu, S Sarangi, J Tuck, J Torrellas
Proceedings of the 19th annual international conference on Supercomputing …, 2005
System and method for non-uniform cache in a multi-core processor
C Hughes, J Tuck, V Lee, Y Chen
US Patent App. 11/023,925, 2006
Hiding the long latency of persist barriers using speculative execution
S Shin, J Tuck, Y Solihin
Proceedings of the 44th Annual International Symposium on Computer …, 2017
SoftSig: software-exposed hardware signatures for code analysis and optimization
J Tuck, W Ahn, L Ceze, J Torrellas
ACM SIGOPS Operating Systems Review 42 (2), 145-156, 2008
Energy-efficient thread-level speculation
J Renau, K Strauss, L Ceze, W Liu, SR Sarangi, J Tuck, J Torrellas
IEEE Micro 26 (1), 80-91, 2006
HAQu: Hardware-accelerated queueing for fine-grained threading on a chip multiprocessor
S Lee, D Tiwari, Y Solihin, J Tuck
2011 IEEE 17th International Symposium on High Performance Computer …, 2011
Efficiently exploiting memory level parallelism on asymmetric coupled cores in the dark silicon era
G Patsilaras, NK Choudhary, J Tuck
ACM Transactions on Architecture and Code Optimization (TACO) 8 (4), 1-21, 2012
The bulk multicore architecture for improved programmability
J Torrellas, L Ceze, J Tuck, C Cascaval, P Montesinos, W Ahn, ...
Communications of the ACM 52 (12), 58-65, 2009
Efficient checkpointing of loop-based codes for non-volatile main memory
H Elnawawy, M Alshboul, J Tuck, Y Solihin
2017 26th International Conference on Parallel Architectures and Compilation …, 2017
CAVA: Hiding L2 misses with checkpoint-assisted value prediction
L Ceze, K Strauss, J Tuck, J Renau, J Torrellas
IEEE Computer Architecture Letters 3 (1), 7-7, 2004
Mmt: Exploiting fine-grained parallelism in dynamic memory management
D Tiwari, S Lee, J Tuck, Y Solihin
2010 IEEE International Symposium on Parallel & Distributed Processing …, 2010
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