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Russell Tessier
Russell Tessier
Bestätigte E-Mail-Adresse bei umass.edu - Startseite
Titel
Zitiert von
Zitiert von
Jahr
FPGA architecture: Survey and challenges
I Kuon, R Tessier, J Rose
Foundations and Trends® in Electronic Design Automation 2 (2), 135-253, 2008
9182008
Reconfigurable computing for digital signal processing: A survey
R Tessier, W Burleson
Journal of VLSI signal processing systems for signal, image and video …, 2001
5742001
Virtual interconnections for reconfigurable logic systems
A Agarwal, J Babb, R Tessier
US Patent 5,596,742, 1997
3091997
Virtual interconnections for reconfigurable logic systems
A Agarwal, J Babb, R Tessier
US Patent 5,761,484, 1998
2981998
Reconfigurable computing architectures
R Tessier, K Pocek, A DeHon
Proceedings of the IEEE 103 (3), 332-354, 2015
2632015
aSOC: A scalable, single-chip communications architecture
J Liang, S Swaminathan, R Tessier
Proceedings 2000 International Conference on Parallel Architectures and …, 2000
2602000
Virtual wires: Overcoming pin limitations in FPGA-based logic emulators
J Babb, R Tessier, A Agarwal
[1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines, 142-151, 1993
2491993
Logic emulation with virtual wires
J Babb, R Tessier, M Dahl, SZ Hanono, DM Hoki, A Agarwal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1997
2271997
Balancing logic utilization and area efficiency in FPGAs
R Tessier, H Giza
International Workshop on Field Programmable Logic and Applications, 535-544, 2000
1642000
FPGA side channel attacks without physical access
C Ramesh, SB Patil, SN Dhanuskodi, G Provelengios, S Pillement, ...
2018 IEEE 26th Annual International Symposium on Field-Programmable Custom …, 2018
1512018
Floating point unit generation and evaluation for FPGAs
J Liang, R Tessier, O Mencer
11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines …, 2003
1502003
An architecture and compiler for scalable on-chip communication
J Liang, A Laffely, S Srinivasan, R Tessier
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 12 (7), 711-726, 2004
1202004
Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits
A Maheshwari, W Burleson, R Tessier
IEEE transactions on very large scale integration (VLSI) systems 12 (3), 299-311, 2004
1142004
A dynamically reconfigurable adaptive viterbi decoder
S Swaminathan, R Tessier, D Goeckel, W Burleson
Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field …, 2002
1122002
Tolerating operational faults in cluster-based FPGAs
V Lakamraju, R Tessier
Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field …, 2000
1082000
FlexGrip: A soft GPGPU for FPGAs
K Andryc, M Merchant, R Tessier
2013 International Conference on Field-Programmable Technology (FPT), 230-237, 2013
1022013
BDD-based logic synthesis for LUT-based FPGAs
N Vemuri, P Kalla, R Tessier
ACM Transactions on Design Automation of Electronic Systems (TODAES) 7 (4 …, 2002
1022002
Multicore soft error rate stabilization using adaptive dual modular redundancy
R Vadlamani, J Zhao, W Burleson, R Tessier
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010
1002010
HAL—The missing piece of the puzzle for hardware reverse engineering, Trojan detection and insertion
M Fyrbiak, S Wallat, P Swierczynski, M Hoffmann, S Hoppach, M Wilhelm, ...
IEEE Transactions on Dependable and Secure Computing 16 (3), 498-510, 2018
922018
BIST-based delay path testing in FPGA architectures
IG Harris, PR Menon, R Tessier
Proceedings International Test Conference 2001 (Cat. No. 01CH37260), 932-938, 2001
862001
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