Giacomo Gabrielli
Giacomo Gabrielli
Principal Research Engineer, ARM
Verified email at arm.com
Title
Cited by
Cited by
Year
The ARM Scalable Vector Extension
N Stephens, S Biles, M Boettcher, J Eapen, M Eyole, G Gabrielli, ...
IEEE Micro 37 (2), 26-39, 2017
992017
Analysis of static and dynamic energy consumption in NUCA caches: Initial results
A Bardine, P Foglia, G Gabrielli, CA Prete
Proceedings of the 2007 workshop on MEmory performance: DEaling with …, 2007
492007
Leveraging data promotion for low power D-NUCA caches
A Bardine, M Comparetti, P Foglia, G Gabrielli, CA Prete, P Stenström
Digital System Design Architectures, Methods and Tools, 2008. DSD'08. 11th …, 2008
332008
Way adaptable D-NUCA caches
A Bardine, M Comparetti, P Foglia, G Gabrielli, C Prete
International Journal of High Performance Systems Architecture 2 (3-4), 215-228, 2010
292010
A power-efficient migration mechanism for D-NUCA caches
A Bardine, M Comparetti, P Foglia, G Gabrielli, CA Prete
2009 Design, Automation & Test in Europe Conference & Exhibition, 598-601, 2009
222009
Improving power efficiency of D-NUCA caches
A Bardine, P Foglia, G Gabrielli, CA Prete, P Stenström
ACM SIGARCH Computer Architecture News 35 (4), 53-58, 2007
222007
Impact of on-chip network parameters on NUCA cache performances
A Bardine, M Comparetti, P Foglia, G Gabrielli, CA Prete
IET computers & digital techniques 3 (5), 501-512, 2009
92009
MALEC: A multiple access low energy cache
M Boettcher, G Gabrielli, BM Al-Hashimi, D Kershaw
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 368-373, 2013
82013
Data processing apparatus and method for performing segmented operations
M Eyole-monono, AD Reid, ML Böttcher, G Gabrielli
US Patent 9,557,995, 2017
72017
Advanced SIMD: Extending the reach of contemporary SIMD architectures
M Boettcher, BM Al-Hashimi, M Eyole, G Gabrielli, A Reid
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-4, 2014
72014
Reducing sensitivity to noc latency in nuca caches
P Foglia, G Gabrielli, F Panicucci, M Solinas
3rd Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip, 2009
52009
Performance sensitivity of NUCA caches to on-chip network parameters
A Bardine, M Comparetti, P Foglia, G Gabrielli, CA Prete
Computer Architecture and High Performance Computing, 2008. SBAC-PAD'08 …, 2008
52008
On-Chip Networks: Impact on the Performance of NUCA Caches
A Bardine, M Comparetti, P Foglia, G Gabrielli, CA Prete
Proceedings of the 11th EUROMICRO Conference on Digital System Design 43, 2008
32008
Implementation Issues of Way Adaptable D-NUCA Caches
A Bardine, M Comparetti, P Foglia, G Gabrielli, CA Prete
Proceedings of the Poster Session of the 4th International Summer School on …, 2008
22008
Applicazione della tecnica di riconfigurazione way-adapting alla progettazione di cache D-NUCA
G Gabrielli
University of Pisa, 2006
12006
Handling exceptional conditions for vector arithmetic instruction
G Gabrielli, NJ Stephens
US Patent 10,776,124, 2020
2020
Data processing apparatus and method for processing vector operands
M Boettcher, M Eyole-monono, G Gabrielli
US Patent 10,514,919, 2019
2019
Speculation barrier instruction
RR Grisenthwaite, G Gabrielli, MJ Horsnell
US Patent App. 16/208,701, 2019
2019
Data processing apparatus and method for performing scan operations
ML Boettcher, M Eyole-monono, G Gabrielli
US Patent 9,355,061, 2016
2016
Performance and power optimizations for non-uniform cache memories
G Gabrielli
University of Pisa, 2010
2010
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