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Jürgen Scheible
Jürgen Scheible
Professor of EDA, Reutlingen University
Verified email at reutlingen-university.de - Homepage
Title
Cited by
Cited by
Year
Automation of analog IC layout: Challenges and solutions
J Scheible, J Lienig
Proceedings of the 2015 Symposium on International Symposium on Physical …, 2015
662015
Reliability-driven layout decompaction for electromigration failure avoidance in complex mixed-signal IC designs
G Jerke, J Lienig, J Scheible
Proceedings of the 41st Annual Design Automation Conference, 181-184, 2004
222004
Using drones for art and exergaming
J Scheible, M Funk, KC Pucihar, M Kljun, M Lochrie, P Egglestone, P Skrlj
IEEE Pervasive Computing 16 (1), 48-56, 2017
212017
Fundamentals of layout design for electronic circuits
J Lienig, J Scheible
Springer, 2020
172020
Lithography hotspots detection using deep learning
V Borisov, J Scheible
2018 15th International Conference on Synthesis, Modeling, Analysis and …, 2018
162018
Heat Generation in Bond Wires
CC Jung, J Scheible
IEEE Transactions on Components, Packaging and Manufacturing Technology 5 …, 2015
142015
PCDS: A New Approach for the Development of Circuit Generators in Analog IC Design
D Marolt, M Greif, J Scheible, G Jerke
Austrian Workshop on Microelectronics (Austrochip) 22, 5-10, 2014
142014
The need and opportunities of electromigration-aware integrated circuit design
S Bigalke, J Lienig, G Jerke, J Scheible, R Jancke
2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2018
122018
SWARM: a self-organization approach for layout automation in analog IC design
D Marolt, J Scheible, G Jerke, V Marolt
International journal of electronics and electrical engineering 4 (5), 374-385, 2016
112016
Die Lösung des feldtheoretischen Viermedienproblems ebener Schichten
J Scheible
Archiv für Elektrotechnik 75 (1), 9-17, 1991
101991
A generic topology selection method for analog circuits with embedded circuit sizing demonstrated on the OTA example
A Gerlach, J Scheible, T Rosahl, FT Eitrich
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017
92017
The Application of layout module generators upon circuit structure recognition
D Marolt, J Scheible, G Jerke
Proc. CDNLive! EMEA 2011, 2011
82011
Der Bond-Rechner–ein Werkzeug zur Dimensionierung von Bonddrähten
A Gerlach, D Marolt, J Scheible
Zuverlässigkeit und Entwurf: 6. GMM-GI-ITG-Fachtagung vom 25. bis 27 …, 2012
72012
A generic procedural generator for sizing of analog integrated circuits
M Schweikardt, Y Uhlmann, F Leber, J Scheible, H Habal
2019 15th Conference on Ph. D Research in Microelectronics and Electronics …, 2019
62019
Research on data augmentation for lithography hotspot detection using deep learning
V Borisov, J Scheible
34th European Mask and Lithography Conference 10775, 204-209, 2018
62018
A generic topology selection method for analog circuits demonstrated on the OTA example
A Gerlach, J Scheible, T Rosahl, FT Eitrich
2015 11th Conference on Ph. D. Research in Microelectronics and Electronics …, 2015
62015
Improvement of simulation-based analog circuit sizing using design-space transformation
M Schweikardt, J Scheible
SMACD/PRIME 2021; International Conference on SMACD and 16th Conference on …, 2021
52021
gPCDS: An interactive tool for creating schematic module generators in analog IC design
M Greif, D Marolt, J Scheible
2016 12th Conference on Ph. D. Research in Microelectronics and Electronics …, 2016
52016
Analog layout automation via self-organization: enhancing the novel SWARM approach
D Marolt, J Scheible, G Jerke, V Marolt
2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS), 55-58, 2016
52016
Thermische Simulation von Bonddrähten in verpackten Chips unter Berücksichtigung der Draht-Package-Interaktion
CC Jung, C Silber, J Scheible
ASIM-Workshop STS/GMMS, 37-47, 2014
52014
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