| eBrainII: a 3 kW realtime custom 3D DRAM integrated ASIC implementation of a biologically plausible model of a human scale cortex D Stathis, C Sudarshan, Y Yang, M Jung, C Weis, A Hemani, A Lansner, ... Journal of Signal Processing Systems 92, 1323-1343, 2020 | 16 | 2020 |
| RiBoSOM: Rapid bacterial genome identification using self-organizing map implemented on the synchoros SiLago platform Y Yang, D Stathis, P Sharma, K Paul, A Hemani, M Grabherr, R Ahmad Proceedings of the 18th International Conference on Embedded Computer …, 2018 | 15 | 2018 |
| A memristor model with concise window function for spiking brain-inspired computation J Xu, D Wang, F Li, L Zhang, D Stathis, Y Yang, Y Jin, A Lansner, ... 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits …, 2021 | 9 | 2021 |
| Optimizing BCPNN learning rule for memory access Y Yang, D Stathis, R Jordão, A Hemani, A Lansner Frontiers in Neuroscience 14, 572269, 2020 | 9 | 2020 |
| Mapping the BCPNN learning rule to a memristor model D Wang, J Xu, D Stathis, L Zhang, F Li, A Lansner, A Hemani, Y Yang, ... Frontiers in Neuroscience 15, 750458, 2021 | 8 | 2021 |
| Approximate Computing Applied to Bacterial Genome Identification using Self-Organizing Maps D Stathis, Y Yang, S Tewari, A Hemani, K Paul, M Grabherr, R Ahmad 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 560-567, 2019 | 6 | 2019 |
| A FPGA-based Hardware Accelerator for Bayesian Confidence Propagation Neural Network L Liu, D Wang, Y Wang, A Lansner, A Hemani, Y Yang, X Hu, Z Zou, ... 2020 IEEE Nordic Circuits and Systems Conference (NorCAS), 1-6, 2020 | 5 | 2020 |
| Vesyla-II: An Algorithm Library Development Tool for Synchoros VLSI Design Style Y Yang, A Hemani arXiv preprint arXiv:2206.07984, 2022 | 2 | 2022 |
| High-Level Synthesis for SiLago: Advances in Optimization of High-Level Synthesis Tool and Neural Network Algorithms Y Yang KTH Royal Institute of Technology, 2022 | 2 | 2022 |
| Scheduling persistent and fully cooperative instructions Y Yang, A Hemani, K Paul 2021 24th Euromicro Conference on Digital System Design (DSD), 229-237, 2021 | 2 | 2021 |
| Reducing the configuration overhead of the distributed two-level control system Y Yang, D Stathis, A Hemani 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 104-107, 2022 | 1 | 2022 |
| Design and implementation of optimized register file for streaming applications AK Patan, D Stathis, P Dhilleswararao, Y Yang, S Boppu, A Hemani 2021 25th International Symposium on VLSI Design and Test (VDAT), 1-4, 2021 | 1 | 2021 |
| MTP-caffe: memory, timing, and power aware tool for mapping CNNs to GPUs Y Yang, SMAH Jafri, A Hemani, D Stathis Proceedings of the 8th Workshop and 6th Workshop on Parallel Programming and …, 2017 | 1 | 2017 |
| FPGA-Based HPC for Associative Memory System D Wang, Y Wang, Y Yang, D Stathis, A Hemani, A Lansner, J Xu, ... 2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC), 52-57, 2024 | | 2024 |
| Efficient Implementation of 2-D Convolution on DRRA and DiMArch Architectures P Dhilleswararao, R Ryansh, S Boppu, Y Yang, A Hemani Proceedings of the 13th International Symposium on Highly Efficient …, 2023 | | 2023 |
| Approximate computation of post-synaptic spikes reduces bandwidth to synaptic storage in a model of cortex D Stathis, Y Yang, A Hemani, A Lansner 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 685-688, 2021 | | 2021 |
