| Soft-error detection using control flow assertions O Goloubeva, M Rebaudengo, MS Reorda, M Violante Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI …, 2003 | 311 | 2003 |
| Soft-error detection through software fault-tolerance techniques M Rebaudengo, MS Reorda, M Torchiano, M Violante Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance …, 1999 | 218 | 1999 |
| A new reliability-oriented place and route algorithm for SRAM-based FPGAs L Sterpone, M Violante IEEE Transactions on Computers 55 (6), 732-744, 2006 | 189 | 2006 |
| Software-implemented hardware fault tolerance O Goloubeva, M Rebaudengo, MS Reorda, M Violante Springer Science & Business Media, 2006 | 188 | 2006 |
| Low power BIST via non-linear hybrid cellular automata F Corno, M Rebaudengo, MS Reorda, G Squillero, M Violante Proceedings 18th IEEE VLSI Test Symposium, 29-34, 2000 | 166 | 2000 |
| Identification and classification of single-event upsets in the configuration memory of SRAM-based FPGAs M Ceschia, M Violante, MS Reorda, A Paccagnella, P Bernardi, ... IEEE Transactions on Nuclear Science 50 (6), 2088-2094, 2003 | 162 | 2003 |
| Analysis of the robustness of the TMR architecture in SRAM-based FPGAs L Sterpone, M Violante IEEE Transactions on Nuclear Science 52 (5), 1545-1549, 2005 | 161 | 2005 |
| Experimentally evaluating an automatic approach for generating safety-critical software with respect to transient errors P Cheynet, B Nicolescu, R Velazco, M Rebaudengo, MS Reorda, ... IEEE Transactions on Nuclear Science 47 (6), 2231-2236, 2000 | 141 | 2000 |
| A new partial reconfiguration-based fault-injection system to evaluate SEU effects in SRAM-based FPGAs L Sterpone, M Violante IEEE Transactions on Nuclear Science 54 (4), 965-970, 2007 | 140 | 2007 |
| A source-to-source compiler for generating dependable software M Rebaudengo, MS Reorda, M Violante, M Torchiano Proceedings First IEEE International Workshop on Source Code Analysis and …, 2001 | 137 | 2001 |
| Evaluating the effects of SEUs affecting the configuration memory of an SRAM-based FPGA M Bellato, P Bernardi, D Bortolato, A Candelori, M Ceschia, ... Proceedings Design, Automation and Test in Europe Conference and Exhibition …, 2004 | 124 | 2004 |
| An FPGA-based approach for speeding-up fault injection campaigns on safety-critical circuits P Civera, L Macchiarulo, M Rebaudengo, MS Reorda, M Violante Journal of Electronic Testing 18 (3), 261-271, 2002 | 123 | 2002 |
| Virtual interactive e‐learning application: An evaluation of the student satisfaction MG Violante, E Vezzetti Computer Applications in Engineering Education 23 (1), 72-91, 2015 | 120 | 2015 |
| A new analytical approach to estimate the effects of SEUs in TMR architectures implemented through SRAM-based FPGAs L Sterpone, M Violante IEEE Transactions on Nuclear Science 52 (6), 2217-2223, 2005 | 118 | 2005 |
| Exploiting circuit emulation for fast hardness evaluation P Civera, L Macchiarulo, M Rebaudengo, MS Reorda, M Violante IEEE Transactions on Nuclear Science 48 (6), 2210-2216, 2001 | 115 | 2001 |
| On the test of microprocessor IP cores F Corno, MS Reorda, G Squillero, M Violante Proceedings Design, Automation and Test in Europe. Conference and Exhibition …, 2001 | 112 | 2001 |
| A new hardware/software platform and a new 1/E neutron source for soft error studies: Testing FPGAs at the ISIS facility M Violante, L Sterpone, A Manuzzato, S Gerardin, P Rech, M Bagatin, ... IEEE Transactions on Nuclear Science 54 (4), 1184-1189, 2007 | 104 | 2007 |
| A new hybrid fault detection technique for systems-on-a-chip P Bernardi, LMV Bolzani, M Rebaudengo, MS Reorda, FL Vargas, ... IEEE transactions on Computers 55 (2), 185-198, 2006 | 99 | 2006 |
| Implementing a new approach for the design of an e‐learning platform in engineering education MG Violante, E Vezzetti Computer Applications in Engineering Education 22 (4), 708-727, 2014 | 96 | 2014 |
| Kano qualitative vs quantitative approaches: An assessment framework for products attributes analysis MG Violante, E Vezzetti Computers in industry 86, 15-25, 2017 | 94 | 2017 |
Matteo SONZA REORDAPolitecnico di Torino, Dept. of Control and Computer EngineeringVerified email at polito.it
