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Peter Cappello
Peter Cappello
Professor of Computer Science, University of California, Santa Barbara
Verified email at cs.ucsb.edu
Title
Cited by
Cited by
Year
Javelin: Internet‐based parallel computing using Java
BO Christiansen, P Cappello, MF Ionescu, MO Neary, KE Schauser, D Wu
Concurrency: Practice and Experience 9 (11), 1139-1160, 1997
3701997
Unifying VLSI Array Designs with Geometric Transformations.
PR Cappello, K Steiglitz
ICPP, 448-457, 1983
1651983
Unifying VLSI array design with linear transformations of space-time
PR Cappello, K Steiglitz
Advances in computing research 2, 23-65, 1984
1521984
Some complexity issues in digital signal processing
P Cappello, K Steiglitz
IEEE Transactions on Acoustics, Speech, and Signal Processing 32 (5), 1037-1041, 1984
1311984
Javelin++ Scalability Issues in Global Computing
MO Neary, SP Brydon, P Kmiec, S Rollins, P Cappello
Proceedings of the ACM 1999 conference on Java Grande, 171-180, 1999
1261999
Javelin 2.0: Java-based parallel computing on the Internet
MO Neary, A Phipps, S Richman, P Cappello
Euro-Par 2000 Parallel Processing: 6th International Euro-Par Conference …, 2000
1082000
Systolic super summation device
PR Cappello, WL Miranker
US Patent 4,751,665, 1988
1011988
Easily testable iterative logic arrays
CW Wu, PR Cappello
IEEE Transactions on Computers 39 (5), 640-652, 1990
971990
Systolic architectures for vector quantization
GA Davidson, PR Cappello, A Gersho
IEEE Transactions on Acoustics, Speech, and Signal Processing 36 (10), 1651-1664, 1988
971988
Advanced eager scheduling for Java-based adaptively parallel computing
MO Neary, P Cappello
Proceedings of the 2002 joint ACM-ISCOPE conference on Java Grande, 56-65, 2002
962002
Javelin: Parallel computing on the internet
MO Neary, BO Christiansen, P Cappello, KE Schauser
Future Generation Computer Systems 15 (5-6), 659-674, 1999
961999
Digital signal processing applications of systolic algorithms
PR Cappello, K Steiglitz
VLSI systems and computations, 245-254, 1981
761981
A VLSI layout for a pipelined Dadda multiplier
PR Cappello, K Steiglitz
ACM Transactions on Computer Systems (TOCS) 1 (2), 157-174, 1983
711983
A processor-time minimal systolic array for transitive closure
CJ Scheiman, PR Cappello
[1990] Proceedings of the International Conference on Application Specific …, 1990
641990
A processor-time minimal systolic array for transitive closure
CJ Scheiman, PR Cappello
[1990] Proceedings of the International Conference on Application Specific …, 1990
641990
Implementing the beam and warming method on the hypercube
J Bruno, PR Cappello
Proceedings of the third conference on Hypercube concurrent computers and …, 1989
591989
Scheduling a system of affine recurrence equations onto a systolic array
Y Yaacoby, PR Cappello
[1988] Proceedings. International Conference on Systolic Arrays, 373-382, 1988
561988
Converting affine recurrence equations to quasi-uniform recurrence equations
Y Yaacoby, PR Cappello
VLSI Algorithms and Architectures: 3rd Aegean Workshop on Computing, AWOC 88 …, 1988
531988
Completely-pipelined architectures for digital signal processing
P Cappello, K Steiglitz
IEEE transactions on acoustics, speech, and signal processing 31 (4), 1016-1023, 1983
501983
Completely-pipelined architectures for digital signal processing
P Cappello, K Steiglitz
IEEE transactions on acoustics, speech, and signal processing 31 (4), 1016-1023, 1983
501983
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