| Single-event transient pulse quenching in advanced CMOS logic circuits JR Ahlbin, LW Massengill, BL Bhuva, B Narasimham, MJ Gadlage, ... IEEE Transactions on Nuclear Science 56 (6), 3050-3056, 2009 | 199 | 2009 |
| Effect of well and substrate potential modulation on single event pulse shape in deep submicron CMOS S DasGupta, AF Witulski, BL Bhuva, ML Alles, RA Reed, OA Amusan, ... IEEE Transactions on Nuclear Science 54 (6), 2407-2412, 2007 | 131 | 2007 |
| Layout technique for single-event transient mitigation via pulse quenching NM Atkinson, AF Witulski, WT Holman, JR Ahlbin, BL Bhuva, ... IEEE Transactions on Nuclear Science 58 (3), 885-890, 2011 | 123 | 2011 |
| Design techniques to reduce SET pulse widths in deep-submicron combinational logic OA Amusan, LW Massengill, BL Bhuva, S DasGupta, AF Witulski, ... IEEE Transactions on Nuclear Science 54 (6), 2060-2064, 2007 | 123 | 2007 |
| The effect of layout topology on single-event transient pulse quenching in a 65 nm bulk CMOS process JR Ahlbin, MJ Gadlage, DR Ball, AW Witulski, BL Bhuva, RA Reed, ... IEEE Transactions on Nuclear Science 57 (6), 3380-3385, 2010 | 118 | 2010 |
| Scaling trends in SET pulse widths in sub-100 nm bulk CMOS processes MJ Gadlage, JR Ahlbin, B Narasimham, BL Bhuva, LW Massengill, ... IEEE Transactions on Nuclear Science 57 (6), 3336-3341, 2010 | 118 | 2010 |
| Scaling trends in SET pulse widths in sub-100 nm bulk CMOS processes MJ Gadlage, JR Ahlbin, B Narasimham, BL Bhuva, LW Massengill, ... IEEE Transactions on Nuclear Science 57 (6), 3336-3341, 2010 | 118 | 2010 |
| Mitigation techniques for single-event-induced charge sharing in a 90-nm bulk CMOS process OA Amusan, LW Massengill, MP Baze, BL Bhuva, AF Witulski, JD Black, ... IEEE Transactions on device and Materials Reliability 9 (2), 311-317, 2009 | 117 | 2009 |
| Cross-layer modeling and simulation of circuit reliability Y Cao, J Velamala, K Sutaria, MSW Chen, J Ahlbin, IS Esqueda, M Bajura, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013 | 81 | 2013 |
| SEU prediction from SET modeling using multi-node collection in bulk transistors and SRAMs down to the 65 nm technology node L Artola, G Hubert, KM Warren, M Gaillardin, RD Schrimpf, RA Reed, ... IEEE Transactions on Nuclear Science 58 (3), 1338-1346, 2011 | 78 | 2011 |
| Independent measurement of SET pulse widths from N-hits and P-hits in 65-nm CMOS S Jagannathan, MJ Gadlage, BL Bhuva, RD Schrimpf, B Narasimham, ... IEEE Transactions on Nuclear Science 57 (6), 3386-3391, 2010 | 68 | 2010 |
| Effect of multiple-transistor charge collection on single-event transient pulse widths JR Ahlbin, MJ Gadlage, NM Atkinson, B Narasimham, BL Bhuva, ... IEEE Transactions on Device and Materials Reliability 11 (3), 401-406, 2011 | 63 | 2011 |
| Effect of multiple-transistor charge collection on single-event transient pulse widths JR Ahlbin, MJ Gadlage, NM Atkinson, B Narasimham, BL Bhuva, ... IEEE Transactions on Device and Materials Reliability 11 (3), 401-406, 2011 | 63 | 2011 |
| Effect of transistor density and charge sharing on single-event transients in 90-nm bulk CMOS NM Atkinson, JR Ahlbin, AF Witulski, NJ Gaspard, WT Holman, BL Bhuva, ... IEEE Transactions on Nuclear Science 58 (6), 2578-2584, 2011 | 60 | 2011 |
| On-chip measurement of single-event transients in a 45 nm silicon-on-insulator technology TD Loveless, JS Kauppila, S Jagannathan, DR Ball, JD Rowe, ... IEEE Transactions on Nuclear Science 59 (6), 2748-2755, 2012 | 57 | 2012 |
| Single-event transient measurements in nMOS and pMOS transistors in a 65-nm bulk CMOS technology at elevated temperatures MJ Gadlage, JR Ahlbin, B Narasimham, BL Bhuva, LW Massengill, ... IEEE Transactions on Device and Materials Reliability 11 (1), 179-186, 2010 | 52 | 2010 |
| Temperature dependence of digital single-event transients in bulk and fully-depleted SOI technologies MJ Gadlage, JR Ahlbin, V Ramachandran, P Gouker, CA Dinkins, ... IEEE Transactions on Nuclear Science 56 (6), 3115-3121, 2009 | 51 | 2009 |
| Temperature dependence of digital single-event transients in bulk and fully-depleted SOI technologies MJ Gadlage, JR Ahlbin, V Ramachandran, P Gouker, CA Dinkins, ... IEEE Transactions on Nuclear Science 56 (6), 3115-3121, 2009 | 51 | 2009 |
| C-CREST technique for combinational logic SET testing JR Ahlbin, JD Black, LW Massengill, OA Amusan, A Balasubramanian, ... IEEE Transactions on Nuclear Science 55 (6), 3347-3351, 2008 | 50 | 2008 |
| Analysis of soft error rates in combinational and sequential logic and implications of hardening for advanced technologies NN Mahatme, I Chatterjee, BL Bhuva, J Ahlbin, LW Massengill, R Shuler 2010 IEEE International Reliability Physics Symposium, 1031-1035, 2010 | 49 | 2010 |
Ron SchrimpfProfessor of Electrical Engineering, Vanderbilt UniversityVerified email at vanderbilt.edu
