Hoang M. Le
Hoang M. Le
Bestätigte E-Mail-Adresse bei informatik.uni-bremen.de
Titel
Zitiert von
Zitiert von
Jahr
Proving transaction and system-level properties of untimed SystemC TLM designs
D Große, HM Le, R Drechsler
Eighth ACM/IEEE International Conference on Formal Methods and Models for …, 2010
932010
Safety evaluation of automotive electronics using virtual prototypes: State of the art and research challenges
JH Oetjens, N Bannow, M Becker, O Bringmann, A Burger, M Chaari, ...
2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2014
652014
Quantified synthesis of reversible logic
R Wille, HM Le, GW Dueck, D GroBe
2008 Design, Automation and Test in Europe, 1015-1020, 2008
632008
Verifying SystemC using an intermediate verification language and symbolic simulation
HM Le, D Große, V Herdt, R Drechsler
Proceedings of the 50th Annual Design Automation Conference, 1-6, 2013
542013
CRAVE: An advanced constrained random verification environment for SystemC
F Haedicke, HM Le, D Große, R Drechsler
2012 International Symposium on System on Chip (SoC), 1-7, 2012
402012
Automatic TLM fault localization for SystemC
HM Le, D Grosse, R Drechsler
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012
402012
Extensible and configurable RISC-V based virtual prototype
V Herdt, D Groβe, HM Le, R Drechsler
2018 Forum on Specification & Design Languages (FDL), 5-16, 2018
382018
The system verification methodology for advanced TLM verification
MFS Oliveira, C Kuznik, HM Le, D Große, F Haedicke, W Mueller, ...
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware …, 2012
322012
Completeness-driven development
R Drechsler, M Diepenbeck, D Große, U Kühne, HM Le, J Seiter, ...
International Conference on Graph Transformation, 38-50, 2012
272012
Verifying SystemC using intermediate verification language and stateful symbolic simulation
V Herdt, HM Le, D Große, R Drechsler
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
262018
Compiled symbolic simulation for SystemC
V Herdt, HM Le, D Große, R Drechsler
Proceedings of the 35th International Conference on Computer-Aided Design, 1-8, 2016
242016
Verifying Instruction Set Simulators using Coverage-guided Fuzzing*
V Herdt, D Große, HM Le, R Drechsler
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 360-365, 2019
212019
Early Concolic Testing of Embedded Binaries with Virtual Prototypes: A RISC-V Case Study*
V Herdt, D Große, HM Le, R Drechsler
2019 56th ACM/IEEE Design Automation Conference (DAC), 1-6, 2019
182019
Verifying SystemC using stateful symbolic simulation
V Herdt, HM Le, R Drechsler
2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2015
172015
Towards analyzing functional coverage in SystemC TLM property checking
HM Le, D Große, R Drechsler
2010 IEEE International High Level Design Validation and Test Workshop …, 2010
172010
Early SoC security validation by VP-based static information flow analysis
M Hassan, V Herdt, HM Le, D Große, R Drechsler
2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 400-407, 2017
162017
Towards early validation of firmware-based power management using virtual prototypes: A constrained random approach
V Herdt, HM Le, D Große, R Drechsler
2017 Forum on Specification and Design Languages (FDL), 1-8, 2017
162017
Towards formal verification of real-world SystemC TLM peripheral models-a case study
HM Le, V Herdt, D Große, R Drechsler
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2016
152016
CRAVE 2.0: The next generation constrained random stimuli generator for SystemC
HM Le, R Drechsler
DVCon Europe, 2014
142014
Induction-based formal verification of SystemC TLM designs
D Große, HM Le, R Drechsler
2009 10th International Workshop on Microprocessor Test and Verification …, 2009
142009
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