Cristiano Santos
Titel
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Zitiert von
Jahr
8.1 A 4?? 4?? 2 homogeneous scalable 3D network-on-chip circuit with 326MFlit/s 0.66 pJ/b robust and fault-tolerant asynchronous 3D links
P Vivet, Y Thonnart, R Lemaire, E Beigne, C Bernard, F Darve, D Lattard, ...
2016 IEEE International Solid-State Circuits Conference (ISSCC), 146-147, 2016
39*2016
3D Sequential Integration: Application-driven technological achievements and guidelines
P Batude, L Brunet, C Fenouillet-Beranger, F Andrieu, JP Colinge, ...
Electron Devices Meeting (IEDM), 2017 IEEE International, 3.1. 1-3.1. 4, 2017
342017
Retention time measurements and modelling of bit error rates of WIDE I/O DRAM in MPSoCs
C Weis, M Jung, P Ehses, C Santos, P Vivet, S Goossens, M Koedam, ...
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015 …, 2015
282015
Thermal performance of 3D ICs: Analysis and alternatives
C Santos, P Vivet, JP Colonna, P Coudrain, R Reis
3D Systems Integration Conference (3DIC), 2014 International, 1-7, 2014
212014
System-level thermal modeling for 3D circuits: Characterization with a 65nm memory-on-logic circuit
C Santos, P Vivet, D Dutoit, P Garrault, N Peltier, R Reis
3D Systems Integration Conference (3DIC), 2013 IEEE International, 1-6, 2013
162013
A transistor sizing method applied to an automatic layout generation tool
C Santos, G Wilke, C Lazzari, R Reis, JL Güntzel
Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings. 16th …, 2003
162003
Using TSVs for thermal mitigation in 3D circuits: Wish and truth
C Santos, PM Souare, F de Crecy, P Coudrain, JP Colonna, P Vivet, ...
3D Systems Integration Conference (3DIC), 2014 International, 1-8, 2014
142014
Experimental Insights into Thermal Dissipation in TSV-Based 3D Integrated Circuits
P Coudrain, P Souare, S Dumas, C Chancel, A Farcy, D Lattard, ...
IEEE Design & Test of Computers, 1-1, 2016
132016
A New Transistor-Level Layout Generation Strategy for Static CMOS Circuits
C Lazzari, C Santos, R Reis
Electronics, Circuits and Systems, 2006. ICECS'06. 13th IEEE International …, 2006
132006
Multi-bit flip-flop usage impact on physical synthesis
C Santos, R Reis, G Godoi, M Barros, F Duarte
Integrated Circuits and Systems Design (SBCCI), 2012 25th Symposium on, 1-6, 2012
102012
Pascal Vivet, Sven Goossens, Martijn Koedam, Norbert Wehn, Retention time measurements and modelling of bit error rates of WIDE I/O DRAM in MPSoCs
C Weis, M Jung, P Ehses, C Santos
Proceedings of the 2015 Design, Automation & Test in Europe Conference …, 2015
92015
Thermal Measurements on Flip-chipped System-on-Chip Packages with Heat Spreader Integration
R Prieto, JP Colonna, P Coudrain, C Santos, P Vivet, S Cheramy, ...
82015
Thermal performance of CoolCube™ monolithic and TSV-based 3D integration processes
C Santos, P Vivet, S Thuries, O Billoint, JP Colonna, P Coudrain, L Wang
3D Systems Integration Conference (3DIC), 2016 IEEE International, 1-5, 2016
72016
Thermal modeling methodology for efficient system-level thermal analysis
C Santos, P Vivet, G Matter, N Peltier, S Kaiser, R Reis
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 1-4, 2014
52014
Effects of using a pin-to-pin delay model on a library-free transistor/gate sizing scheme
C Santos, D Ferrao, C Lazzari, G Wilke, JL Guntzel, R Reis
48th Midwest Symposium on Circuits and Systems, 2005., 315-318, 2005
52005
Incremental timing optimization for automatic layout generation
C Santos, D Ferrão, R Reis, JL Guntzel
2005 IEEE International Symposium on Circuits and Systems, 3567-3570, 2005
42005
Thermal Aspects and High-Level Explorations of 3D stacked DRAMs
C Weis, M Jung, O Naji, C Santos, P Vivet, A Hansson
2015 IEEE Computer Society Annual Symposium on VLSI, 609-614, 2015
32015
Thermal impact of 3D stacking and die thickness: Analysis and characterization of a memory-on-logic 3D circuit
C Santos, P Vivet, R Reis
Electronics, Circuits and Systems (ICECS), 2014 21st IEEE International …, 2014
32014
Path Delay Fault Test Generation Using Exact Floating Mode Sensitization
D Ferrão, C Santos, G Wilke, R Reis, M Lubaszewsky, J Güntzel
5th LATW, 2004
32004
Transistor Temperature Deviation Analysis in Monolithic 3D Standard Cells
M Brocard, B Mathieu, JP Colonna, C Santos, C Fenouillet-Beranger, ...
VLSI (ISVLSI), 2017 IEEE Computer Society Annual Symposium on, 539-544, 2017
22017
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