Deming Chen
Cited by
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Csrnet: Dilated convolutional neural networks for understanding the highly congested scenes
Y Li, X Zhang, D Chen
Proceedings of the IEEE conference on computer vision and pattern …, 2018
The sixth visual object tracking vot2018 challenge results
M Kristan, A Leonardis, J Matas, M Felsberg, R Pflugfelder, ...
Proceedings of the European conference on computer vision (ECCV) workshops, 0-0, 2018
Springer handbook of automation
SY Nof
Springer Berlin Heidelberg, 2009
DNNBuilder: An automated tool for building high-performance DNN hardware accelerators for FPGAs
X Zhang, J Wang, C Zhu, Y Lin, J Xiong, W Hwu, D Chen
2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2018
3-D nFPGA: A reconfigurable architecture for 3-D CMOS/nanomaterial hybrid digital circuits
C Dong, D Chen, S Haruehanroengra, W Wang
IEEE Transactions on Circuits and Systems I: Regular Papers 54 (11), 2489-2501, 2007
Architecture evaluation for power-efficient FPGAs
F Li, D Chen, L He, J Cong
Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field …, 2003
FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs
A Papakonstantinou, K Gururaj, JA Stratton, D Chen, J Cong, WMW Hwu
2009 IEEE 7th Symposium on Application Specific Processors, 35-42, 2009
Performance and power evaluation of a 3D CMOS/nanomaterial reconfigurable architecture
C Dong, D Chen, S Tanachutiwat, W Wang
2007 IEEE/ACM International Conference on Computer-Aided Design, 758-764, 2007
Reconfigurable circuit design with nanomaterials
C Dong, S Chilstedt, D Chen
2009 Design, Automation & Test in Europe Conference & Exhibition, 442-447, 2009
FPGA design automation: A survey
D Chen, J Cong, P Pan
Foundations and Trends® in Electronic Design Automation 1 (3), 195-330, 2006
DAOmap: A depth-optimal area optimization mapping algorithm for FPGA designs
D Chen, J Cong
IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004 …, 2004
FPGA/DNN co-design: An efficient design methodology for IoT intelligence on the edge
C Hao, X Zhang, Y Li, S Huang, J Xiong, K Rupnow, W Hwu, D Chen
Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019
Power modeling and characteristics of field programmable gate arrays
F Li, Y Lin, L He, D Chen, J Cong
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2005
Compressing large-scale transformer-based models: A case study on bert
P Ganesh, Y Chen, X Lou, MA Khan, Y Yang, H Sajjad, P Nakov, D Chen, ...
Transactions of the Association for Computational Linguistics 9, 1061-1080, 2021
BLESS: bloom filter-based error correction solution for high-throughput sequencing reads
Y Heo, XL Wu, D Chen, J Ma, WM Hwu
bioinformatics 30 (10), 1354-1362, 2014
Low-power high-level synthesis for FPGA architectures
D Chen, J Cong, Y Fan
Proceedings of the 2003 international symposium on Low power electronics and …, 2003
A SPICE-compatible model of graphene nano-ribbon field-effect transistors enabling circuit-level delay and power analysis under process variation
YY Chen, A Rogachev, A Sangai, G Iannaccone, G Fiori, D Chen
Proceedings of the Conference on Design, Automation and Test in Europe, 1789 …, 2013
Accelerating distributed reinforcement learning with in-switch computing
Y Li, IJ Liu, Y Yuan, D Chen, A Schwing, J Huang
Proceedings of the 46th International Symposium on Computer Architecture …, 2019
An efficient compiler framework for cache bypassing on GPUs
X Xie, Y Liang, G Sun, D Chen
2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 516-523, 2013
Cloud-DNN: An open framework for mapping DNN models to cloud FPGAs
Y Chen, J He, X Zhang, C Hao, D Chen
Proceedings of the 2019 ACM/SIGDA international symposium on field …, 2019
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