Somayeh Timarchi
Somayeh Timarchi
Lecturer, University of hertfordshire - Shahid Beheshti University - TUDelft
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Low-power and fast full adder by exploring new XOR and XNOR gates
H Naseri, S Timarchi
IEEE transactions on very large scale integration (VLSI) systems 26 (8 …, 2018
Efficient Reverse Converter Designs for the New 4-Moduli Sets and Based on New CRTs
AS Molahosseini, K Navi, C Dadkhah, O Kavehei, S Timarchi
IEEE Transactions on Circuits and Systems I: Regular Papers 57 (4), 823-835, 2009
A novel low-power full-adder cell for low voltage
K Navi, M Maeen, V Foroutan, S Timarchi, O Kavehei
Integration 42 (4), 457-467, 2009
Arithmetic circuits of redundant SUT-RNS
S Timarchi, K Navi
IEEE Transactions on instrumentation and measurement 58 (9), 2959-2968, 2009
An ultra-low-power 9T SRAM cell based on threshold voltage techniques
M Moghaddam, S Timarchi, MH Moaiyeri, M Eshghi
Circuits, Systems, and Signal Processing 35, 1437-1455, 2016
Efficient class of redundant residue number system
S Timarchi, K Navi
2007 IEEE international symposium on intelligent signal processing, 1-6, 2007
New Design of RNS Subtractor for modulo 2n+ 1
S Timarchi, K Navi, M Hosseinzade
2006 2nd International Conference on Information & Communication …, 2006
Area–time–power efficient FFT architectures based on binary-signed-digit CORDIC
H Mahdavi, S Timarchi
IEEE Transactions on Circuits and Systems I: Regular Papers 66 (10), 3874-3881, 2019
Improved modulo 2n+ 1 adder design
S Timarchi, K Navi
International Journal of Electrical and Computer Engineering 2 (3), 472-479, 2008
Low-power DCT-based compressor for wireless capsule endoscopy
A Shabani, S Timarchi
Signal Processing: Image Communication 59, 83-95, 2017
High-speed energy-efficient 5: 2 compressor
A Najafi, S Timarchi, A Najafi
2014 37th international convention on information and communication …, 2014
Improving architectures of binary signed-digit CORDIC with generic/specific initial angles
H Mahdavi, S Timarchi
IEEE Transactions on Circuits and Systems I: Regular Papers 67 (7), 2297-2304, 2020
A novel high-speed low-power binary signed-digit adder
S Timarchi, P Ghayour, A Shahbahrami
The 16th CSI International Symposium on Computer Architecture and Digital …, 2012
Two efficient approximate unsigned multipliers by developing new configuration for approximate 4: 2 compressors
L Sayadi, S Timarchi, A Sheikh-Akbari
IEEE Transactions on Circuits and Systems I: Regular Papers 70 (4), 1649-1659, 2023
Generalised fault-tolerant stored-unibit-transfer residue number system multiplier for moduli set {2n− 1, 2n, 2n+ 1}
S Timarchi, M Fazlali
IET computers & digital techniques 6 (5), 269-276, 2012
A unified addition structure for moduli set {2n−1, 2n, 2n+1} based on a novel RNS representation
S Timarchi, M Fazlali, SD Cotofana
2010 IEEE International Conference on Computer Design, 247-252, 2010
Fast architecture for decimal digit multiplication
M Fazlali, H Valikhani, S Timarchi, HT Malazi
Microprocessors and Microsystems 39 (4-5), 296-301, 2015
Design of Residue Number System Circuits in Current mode
M Hosseinzadeh, K Navi, S Timarchi
Proc. 14th Iranian Conference of Electrical Engineering, 2006
Efficient approximate multiplier based on a new 1-gate approximate compressor
SAH Ejtahed, S Timarchi
Circuits, Systems, and Signal Processing, 1-20, 2022
Radix-4 implementation of redundant interleaved modular multiplication on FPGA
L Rahimzadeh, M Eshghi, S Timarchi
2014 22nd Iranian Conference on Electrical Engineering (ICEE), 523-526, 2014
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