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Vikram Suresh
Vikram Suresh
ASIC Architect, Block Inc
Verified email at squareup.com
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Cited by
Year
340mV-1.1 V, 289Gbps/W, 2090-gate NanoAES Hardware Accelerator with Area-optimized Encrypt/Decrypt GF (2 4) 2 Polynomials in 22nm tri-gate CMOS
S Mathew, S Satpathy, V Suresh, H Kaul, M Anders, G Chen, A Agarwal, ...
IEEE Symposium on VLSI Circuits, 2014
1572014
RNG: A 300–950 mV, 323 Gbps/W All-Digital Full-Entropy True Random Number Generator in 14 nm FinFET CMOS
SK Mathew, D Johnston, S Satpathy, V Suresh, P Newman, MA Anders, ...
IEEE Journal of Solid-State Circuits 51 (7), 1695-1704, 2016
1162016
μRNG: A 300-950mV 323Gbps/W all-digital full-entropy TRNG in 14nm FinFET CMOS
S Mathew
IEEE Proc. of the ESSCIRC, 116-119, 2015
116*2015
A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS
S Satpathy, SK Mathew, V Suresh, MA Anders, H Kaul, A Agarwal, ...
IEEE Journal of Solid-State Circuits 52 (4), 940-949, 2017
1002017
An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS
SK Satpathy, SK Mathew, R Kumar, V Suresh, MA Anders, H Kaul, ...
IEEE Journal of Solid-State Circuits 54 (4), 1074-1085, 2019
742019
Entropy extraction in metastability-based TRNG
VB Suresh, WP Burleson
Hardware-Oriented Security and Trust (HOST), 2010 IEEE International …, 2010
562010
Entropy and Energy Bounds for Metastability Based TRNG with Lightweight Post-Processing
VB Suresh, WP Burleson
IEEE Transactions on Circuits and Systems I: Regular Papers 62 (7), 1785-1793, 2015
502015
On-chip lightweight implementation of reduced NIST randomness test suite
VB Suresh, D Antonioli, WP Burleson
2013 IEEE International Symposium on Hardware-Oriented Security and Trust …, 2013
342013
Apparatuses and methods for frequency scaling a message scheduler data path of a hashing accelerator
V Suresh, S Mathew, S Satpathy
US Patent 10,928,847, 2021
312021
2.9 TOPS/W Reconfigurable Dense/Sparse Matrix-Multiply Accelerator with Unified INT8/INTI6/FP16 Datapath in 14NM Tri-Gate CMOS
M Anders, H Kaul, S Mathew, V Suresh, S Satpathy, A Agarwal, S Hsu, ...
2018 IEEE Symposium on VLSI Circuits, 39-40, 2018
262018
Implementing hardware trojans: Experiences from a hardware trojan challenge
GT Becker, A Lakshminarasimhan, L Lin, S Srivathsa, VB Suresh, ...
2011 IEEE 29th International Conference on Computer Design (ICCD), 301-304, 2011
252011
A 0.26% BER, 1028 Challenge-Response Machine-Learning Resistant Strong-PUF in 14nm CMOS Featuring Stability-Aware Adversarial Challenge Selection
V Suresh, R Kumar, M Anders, H Kaul, V De, S Mathew
2020 IEEE Symposium on VLSI Circuits, 1-2, 2020
232020
Non-linear physically unclonable function (PUF) circuit with machine-learning attack resistance
VB Suresh, SK Mathew, SK Satpathy
US Patent 10,027,472, 2018
222018
Hardware apparatuses and methods for data decompression
SK Satpathy, JD Guilford, SK Mathew, V Gopal, VB Suresh
US Patent App. 14/757,854, 2019
202019
Hardware apparatuses and methods for data decompression
SK Satpathy, JD Guilford, SK Mathew, V Gopal, VB Suresh
US Patent 10,177,782, 2019
202019
Optimized SHA-256 datapath for energy-efficient high-performance Bitcoin mining
VB Suresh, SK Satpathy, SK Mathew
US Patent 10,142,098, 2018
192018
Energy-efficient bitcoin mining hardware accelerators
VB Suresh, SK Satpathy, SK Mathew
US Patent 10,313,108, 2019
182019
Robust metastability-based TRNG design in nanometer CMOS with sub-vdd pre-charge and hybrid self-calibration
VB Suresh, WP Burleson
Thirteenth International Symposium on Quality Electronic Design (ISQED), 298-305, 2012
172012
A 4900-μmē 839-Mb/s Side-Channel Attack-Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition
R Kumar, V Suresh, M Kar, S Satpathy, MA Anders, H Kaul, A Agarwal, ...
IEEE Journal of Solid-State Circuits, 2020
162020
Techniques for secure message authentication with unified hardware acceleration
VB Suresh, KS Yap, SK Mathew, SK Satpathy
US Patent App. 15/393,196, 2018
162018
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