Raghavan Kumar
Raghavan Kumar
Intel Labs
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A 4096-neuron 1M-synapse 3.8-pJ/SOP spiking neural network with on-chip STDP learning and sparse weights in 10-nm FinFET CMOS
GK Chen, R Kumar, HE Sumbul, PC Knag, RK Krishnamurthy
IEEE Journal of Solid-State Circuits 54 (4), 992-1002, 2018
On design of a highly secure PUF based on non-linear current mirrors
R Kumar, W Burleson
2014 IEEE international symposium on hardware-oriented security and trust …, 2014
Active and passive side-channel attacks on delay based PUF designs
GT Becker, R Kumar
Cryptology ePrint Archive, 2014
Parametric Trojans for Fault-Injection Attacks on Cryptographic Hardware
R Kumar, P Jovanovic, W Burleson, I Polian
Fault Diagnosis and Tolerance in Cryptography (FDTC), 18-28, 2014
An all-digital unified physically unclonable function and true random number generator featuring self-calibrating hierarchical Von Neumann extraction in 14-nm tri-gate CMOS
SK Satpathy, SK Mathew, R Kumar, V Suresh, MA Anders, H Kaul, ...
IEEE Journal of Solid-State Circuits 54 (4), 1074-1085, 2019
Compute in memory circuits with multi-Vdd arrays and/or analog multipliers
HE Sumbul, P Knag, GK Chen, R Kumar, A Sharma, S Manipatruni, ...
US Patent 11,061,646, 2021
Why compete when you can work together: FPGA-ASIC integration for persistent RNNs
E Nurvitadhi, D Kwon, A Jafari, A Boutros, J Sim, P Tomson, H Sumbul, ...
2019 IEEE 27th Annual International Symposium on Field-Programmable Custom …, 2019
A 617-TOPS/W all-digital binary neural network accelerator in 10-nm FinFET CMOS
PC Knag, GK Chen, HE Sumbul, R Kumar, SK Hsu, A Agarwal, M Kar, ...
IEEE journal of solid-state circuits 56 (4), 1082-1092, 2020
On improving reliability of delay based physically unclonable functions under temperature variations
R Kumar, HK Chandrikakutty, S Kundu
2011 IEEE International Symposium on Hardware-Oriented Security and Trust …, 2011
In-memory multiply and accumulate with global charge-sharing
HE Sumbul, GK Chen, R Kumar, P Knag, A Sharma, S Manipatruni, ...
US Patent 10,748,603, 2020
On design of temperature invariant physically unclonable functions based on ring oscillators
R Kumar, VC Patil, S Kundu
2012 IEEE Computer Society Annual Symposium on VLSI, 165-170, 2012
Side-Channel Assisted Modeling Attacks on Feed-Forward Arbiter PUFs Using Silicon Data
R Kumar, W Burleson
Radio Frequency Identification. Security and Privacy Issues 9440, 53-67, 2015
A 0.26% BER, 1028 Challenge-Response Machine-Learning Resistant Strong-PUF in 14nm CMOS Featuring Stability-Aware Adversarial Challenge Selection
V Suresh, R Kumar, M Anders, H Kaul, V De, S Mathew
2020 IEEE Symposium on VLSI Circuits, 1-2, 2020
Protecting cryptographic hardware against malicious attacks by nonlinear robust codes
V Tomashevich, Y Neumeier, R Kumar, O Keren, I Polian
Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 40-45, 2014
Binary, ternary and bit serial compute-in-memory circuits
P Knag, GK Chen, R Kumar, HE Sumbul, A Sharma, S Manipatruni, ...
US Patent 10,642,922, 2020
Compute in memory circuits with time-to-digital computation
R Kumar, P Knag, GK Chen, HE Sumbul, S Manipatruni, A Mathuriya, ...
US Patent 11,048,434, 2021
Precise fault-injections using voltage and temperature manipulation for differential cryptanalysis
R Kumar, P Jovanovic, I Polian
IEEE International Online Testing Symposium (IOLTS), 43-48, 2014
Neuromorphic computer with reconfigurable memory mapping for various neural network topologies
GK Chen, R Kumar, HE Sumbul, P Knag, RK Krishnamurthy
US Patent 11,062,203, 2021
Neural network with reconfigurable sparse connectivity and online learning
HE Sumbul, GK Chen, R Kumar, P Knag, RK Krishnamurthy
US Patent 10,713,558, 2020
A high-speed cryogenic SiGe channel combiner IC for large photon-starved SNSPD arrays
JC Bardin, P Ravindran, SW Chang, R Kumar, JA Stern, MD Shaw, ...
Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 2013 IEEE, 215-218, 2013
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