Bogdan Pasca
Titel
Zitiert von
Zitiert von
Jahr
Designing custom arithmetic data paths with FloPoCo
F De Dinechin, B Pasca
IEEE Design & Test of Computers 28 (4), 18-27, 2011
2712011
An FPGA-specific approach to floating-point accumulation and sum-of-products
F De Dinechin, B Pasca, O Cret, R Tudoran
2008 International Conference on Field-Programmable Technology, 33-40, 2008
882008
Multipliers for floating-point double precision and beyond on FPGAs
S Banescu, F De Dinechin, B Pasca, R Tudoran
ACM SIGARCH Computer Architecture News 38 (4), 73-79, 2011
772011
Large multipliers with fewer DSP blocks
F de Dinechin, B Pasca
2009 International Conference on Field Programmable Logic and Applications …, 2009
712009
Generating high-performance custom floating-point pipelines
F De Dinechin, C Klein, B Pasca
2009 International Conference on Field Programmable Logic and Applications …, 2009
702009
Automatic generation of polynomial-based hardware architectures for function evaluation
F De Dinechin, M Joldes, B Pasca
ASAP 2010-21st IEEE International Conference on Application-specific Systems …, 2010
562010
Floating-point DSP block architecture for FPGAs
M Langhammer, B Pasca
Proceedings of the 2015 ACM/SIGDA International Symposium on Field …, 2015
512015
Large multipliers with less DSP blocks
F De Dinechin, B Pasca
482009
Floating-point exponential functions for DSP-enabled FPGAs
F De Dinechin, B Pasca
2010 International Conference on Field-Programmable Technology, 110-117, 2010
452010
Pipelined FPGA adders
F De Dinechin, HD Nguyen, B Pasca
2010 International Conference on Field Programmable Logic and Applications …, 2010
382010
Correctly rounded floating-point division for DSP-enabled FPGAs
B Pasca
22nd International Conference on Field Programmable Logic and Applications …, 2012
352012
Multiplicative square root algorithms for FPGAs
F De Dinechin, M Joldes, B Pasca, G Revy
2010 International Conference on Field Programmable Logic and Applications …, 2010
282010
FPGA-specific arithmetic optimizations of short-latency adders
HD Nguyen, B Pasca, TB Preußer
2011 21st International Conference on Field Programmable Logic and …, 2011
212011
FPGA-specific synthesis of loop-nests with pipelined computational cores
C Alias, B Pasca, A Plesco
Microprocessors and Microsystems 36 (8), 606-619, 2012
192012
Floating-point exponentiation units for reconfigurable computing
F De Dinechin, P Echeverria, M López-Vallejo, B Pasca
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 6 (1), 1-15, 2013
142013
Design and implementation of an embedded FPGA floating point DSP block
M Langhammer, B Pasca
2015 IEEE 22nd Symposium on Computer Arithmetic, 26-33, 2015
132015
Design and implementation of an embedded FPGA floating point DSP block
M Langhammer, B Pasca
2015 IEEE 22nd Symposium on Computer Arithmetic, 26-33, 2015
132015
Custom arithmetic datapath design for FPGAs using the FloPoCo core generator
F De Dinechin, B Pasca, E Normale
Design & Test of Computers, IEEE 28 (4), 18-27, 2011
132011
High-performance qr decomposition for fpgas
M Langhammer, B Pasca
Proceedings of the 2018 ACM/SIGDA International Symposium on Field …, 2018
112018
An FPGA architecture for solving the Table Maker's Dilemma
F De Dinechin, JM Muller, B Pasca, A Plesco
ASAP 2011-22nd IEEE International Conference on Application-specific Systems …, 2011
112011
Das System kann den Vorgang jetzt nicht ausführen. Versuchen Sie es später erneut.
Artikel 1–20