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Sorin Cotofana
Sorin Cotofana
Quantum & Computer Engineering, Delft University of Technology
Bestätigte E-Mail-Adresse bei tudelft.nl - Startseite
Titel
Zitiert von
Zitiert von
Jahr
The 2021 magnonics roadmap
A Barman, G Gubbiotti, S Ladak, AO Adeyeye, M Krawczyk, J Gräfe, ...
Journal of Physics: Condensed Matter 33 (41), 413001, 2021
2072021
The MOLEN ρμ-coded processor
S Vassiliadis, S Wong, S Cotöfană
Field-Programmable Logic and Applications: 11th International Conference …, 2001
1482001
Introduction to spin wave computing
A Mahmoud, F Ciubotaru, F Vanderveken, AV Chumak, S Hamdioui, ...
Journal of Applied Physics 128 (16), 161101, 2020
1442020
A linear threshold gate implementation in single electron technology
C Lageweg, S Cotofana, S Vassiliadis
Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging …, 2001
1442001
A sum of absolute differences implementation in FPGA hardware
S Wong, S Vassiliadis, S Cotofana
Proceedings. 28th Euromicro Conference, 183-188, 2002
1032002
A magnonic directional coupler for integrated magnonic half-adders
Q Wang, M Kewenig, M Schneider, R Verba, F Kohl, B Heinz, M Geilen, ...
Nature Electronics 3 (12), 765-774, 2020
992020
Single electron encoded latches and flip-flops
C Lageweg, S Cotofana, S Vassiliadis
IEEE Transactions on Nanotechnology 3 (2), 237-248, 2004
902004
A unified aging model of NBTI and HCI degradation towards lifetime reliability management for nanoscale MOSFET circuits
Y Wang, S Cotofana, L Fang
2011 IEEE/ACM International Symposium on Nanoscale Architectures, 175-180, 2011
872011
Determining a coverage mask for a pixel
D Crisu, S Cotofana, S Vassiliadis, P Liuha
US Patent 7,006,110, 2006
822006
Advances in magnetics roadmap on spin-wave computing
AV Chumak, P Kabos, M Wu, C Abert, C Adelmann, AO Adeyeye, ...
IEEE Transactions on Magnetics 58 (6), 1-72, 2022
76*2022
Addition related arithmetic operations via controlled transport of charge
S Cotofana, C Lageweg, S Vassiliadis
IEEE Transactions on Computers 54 (3), 243-256, 2005
662005
2-1 addition and related arithmetic operations with threshold logic
S Vassilladis, S Contofana, K Bertels
Computers, IEEE Transactions on 45 (9), 1062-1067, 1996
571996
Static buffered set based logic gates
C Lageweg, S Cotofana, S Vassiliadis
Proceedings of the 2nd IEEE Conference on Nanotechnology, 491-494, 2002
542002
Field-programmable custom computing machines-a taxonomy
M Sima, S Vassiliadis, S Cotofana, J van Eijndhoven, K Vissers
Field-Programmable Logic and Applications: Reconfigurable Computing Is Going …, 2002
512002
An O (n) residue number system to mixed radix conversion technique
KA Gbolagade, SD Cotofana
2009 IEEE International Symposium on Circuits and Systems, 521-524, 2009
502009
Statistical reliability analysis of NBTI impact on FinFET SRAMs and mitigation technique using independent-gate devices
Y Wang, SD Cotofana, L Fang
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale …, 2012
452012
A full adder implementation using SET based linear threshold gates
C Lageweg, S Cotofana, S Vassiliadis
9th International Conference on Electronics, Circuits and Systems 2, 665-668, 2002
432002
An 8x8 IDCT Implementation on an FPGA-augmented TriMedia
M Sima, S Cotofana, JTJ van Eijndhoven, S Vassiliadis, K Vissers
The 9th Annual IEEE Symposium on Field-Programmable Custom Computing …, 2001
402001
Periodic symmetric functions, serial addition, and multiplication with neural networks
S Cotofana, S Vassiliadis
IEEE Transactions on Neural Networks 9 (6), 1118-1128, 1998
391998
An improved RNS reverse converter for the {22n+1−1, 2n, 2n−1} moduli set
KA Gbolagade, R Chaves, L Sousa, SD Cotofana
Proceedings of 2010 IEEE International Symposium on Circuits and Systems …, 2010
372010
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