| Voltage scheduling problem for dynamically variable voltage processors T Ishihara, H Yasuura Proceedings of the 1998 international symposium on Low power electronics and …, 1998 | 1064 | 1998 |
| High-speed VLSI multiplication algorithm with a redundant binary addition tree Takagi, Yasuura, Yajima IEEE Transactions on Computers 100 (9), 789-796, 1985 | 502 | 1985 |
| A bus delay reduction technique considering crosstalk K Hirose, H Yasuura Proceedings of the conference on Design, automation and test in Europe, 441-445, 2000 | 192 | 2000 |
| A high-performance, pipelined, FPGA-based genetic algorithm machine B Shackleford, G Snider, RJ Carter, E Okushi, M Yasuda, K Seo, ... Genetic Programming and Evolvable Machines 2, 33-60, 2001 | 119 | 2001 |
| Real-time task scheduling for a variable voltage processor T Okuma, T Ishihara, H Yasuura Proceedings 12th International Symposium on System Synthesis, 24-29, 1999 | 115 | 1999 |
| RFID privacy using user-controllable uniqueness S Inoue, H Yasuura | 110 | 2003 |
| On Parallel Computational Complexity of Unification. H Yasuura Unknown Host Publication Title, 235-243, 1984 | 86 | 1984 |
| A novel test methodology for core-based system LSIs and a testing time minimization problem M Sugihara, H Date, H Yasuura Proceedings International Test Conference 1998 (IEEE Cat. No. 98CH36270 …, 1998 | 82 | 1998 |
| The parallel enumeration sorting scheme for VLSI Yasuura, Takagi, Yajima IEEE Transactions on Computers 100 (12), 1192-1201, 1982 | 81 | 1982 |
| Scheduling of page-fetches in join operations TH Merrett, Y Kambayashi, H Yasuura Proceedings of the seventh international conference on Very Large Data Bases …, 1981 | 78 | 1981 |
| Code placement techniques for cache miss rate reduction H Tomiyama, H Yasuura ACM Transactions on Design Automation of Electronic Systems (TODAES) 2 (4 …, 1997 | 75 | 1997 |
| Optimal code placement of embedded software for instruction caches H Tomiyama, H Yasuura Proceedings ED&TC European Design and Test Conference, 96-101, 1996 | 69 | 1996 |
| Analysis and minimization of test time in a combined BIST and external test approach M Sugihara, H Yasuura Proceedings of the conference on Design, automation and test in Europe, 134-140, 2000 | 62 | 2000 |
| A power reduction technique with object code merging for application specific embedded processors T Ishihara, H Yasuura Proceedings of the conference on design, automation and test in Europe, 617-623, 2000 | 59 | 2000 |
| Instruction scheduling for power reduction in processor-based system design H Tomiyama, T Ishihara, A Inoue, H Yasuura Proceedings Design, Automation and Test in Europe, 855-860, 1998 | 54 | 1998 |
| Software energy reduction techniques for variable-voltage processors T Okuma, H Yasuura, T Ishihara IEEE Design & Test of Computers 18 (2), 31-41, 2001 | 53 | 2001 |
| High-speed logic simulation on vector processors N Ishiura, H Yasuura, S Yajima IEEE transactions on computer-aided design of integrated circuits and …, 1987 | 53 | 1987 |
| Smart sensors and systems YL Lin, CM Kyung, H Yasuura, Y Liu Springer International Publishing 12, 467, 2015 | 48* | 2015 |
| A system-level energy minimization approach using datapath width optimization Y Cao, H Yasuura Proceedings of the 2001 international symposium on Low power electronics and …, 2001 | 44 | 2001 |
| An RTOS in hardware for energy efficient software-based TCP/IP processing N Maruyama, T Ishihara, H Yasuura 2010 IEEE 8th symposium on application specific processors (SASP), 58-63, 2010 | 43 | 2010 |
