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Nilmini Abeyratne
Nilmini Abeyratne
Verified email at intel.com - Homepage
Title
Cited by
Cited by
Year
Scaling towards kilo-core processors with asymmetric high-radix topologies
N Abeyratne, R Das, Q Li, K Sewell, B Giridhar, RG Dreslinski, D Blaauw, ...
2013 IEEE 19th International Symposium on High Performance Computer …, 2013
582013
Enhancing dram self-refresh for idle power reduction
B Oh, N Abeyratne, J Ahn, RG Dreslinski, T Mudge
Proceedings of the 2016 International Symposium on Low Power Electronics and …, 2016
112016
Reetuparna Das, Qingkun Li, Korey Sewell, Bharan Giridhar, Ronald G. Dreslinski, David Blaauw, and Trevor Mudge. 2013. Scaling Towards Kilo-core Processors with Asymmetric High …
N Abeyratne
Proceedings of the 2013 IEEE 19th International Symposium on High …, 0
9
Checkpointing exascale memory systems with existing memory technologies
N Abeyratne, HM Chen, B Oh, R Dreslinski, C Chakrabarti, T Mudge
Proceedings of the Second International Symposium on Memory Systems, 18-29, 2016
82016
Single cycle arbitration within an interconnect
S Jeloka, SN Abeyratne, RG Dreslinski, R Das, TN Mudge, DT Blaauw
US Patent 9,514,074, 2016
62016
Enhanced memory device
B Oh, S Abeyratne, RG Dreslinski, T Mudge
US Patent 10,002,657, 2018
42018
SMART: STT-MRAM architecture for smart activation and sensing
B Oh, N Abeyratne, NS Kim, RG Dreslinski, T Mudge
Proceedings of the International Symposium on Memory Systems, 316-330, 2019
22019
Quality-of-service for a high-radix switch
N Abeyratne, S Jeloka, Y Kang, D Blaauw, RG Dreslinski, R Das, ...
Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014
12014
Rethinking DRAM's page mode with STT-MRAM
B Oh, N Abeyratne, NS Kim, J Ahn, RG Dreslinski, T Mudge
IEEE Transactions on Computers, 2022
2022
Apparatus and methods for generating a selection signal to perform an arbitration in a single cycle between multiple signal inputs having respective data to send
S Jeloka, SN Abeyratne, RG Dreslinski, R Das, TN Mudge, DT Blaauw
US Patent 10,037,295, 2018
2018
Studies in Exascale Computer Architecture: Interconnect, Resiliency, and Checkpointing
S Abeyratne
2017
Low Design-Risk Checkpointing Storage Solution for Exascale Supercomputers
N Abeyratne, T Mudge
Network 421, 1.8, 2016
2016
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