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Hussain Al-Asaad
Hussain Al-Asaad
Professor of Electrical and Computer Engineering, UC Davis
Verified email at ucdavis.edu - Homepage
Title
Cited by
Cited by
Year
Online BIST for embedded systems
H Al-Asaad, BT Murray, JP Hayes
IEEE design & Test of Computers 15 (4), 17-24, 1998
1131998
High-level design verification of microprocessors via error modeling
DV Campenhout, H Al-Asaad, JP Hayes, T Mudge, RB Brown
ACM Transactions on Design Automation of Electronic Systems (TODAES) 3 (4 …, 1998
681998
Design verification via simulation and automatic test pattern generation
H Al-Asaad, JP Hayes
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD …, 1995
661995
Automatically generating an input sequence for a circuit design using mutant-based verification
J Campos, H Al-Asaad
US Patent 7,694,253, 2010
352010
On-line built-in self-test for operational faults
H Al-Asaad, M Shringi
2000 IEEE Autotestcon Proceedings. IEEE Systems Readiness Technology …, 2000
282000
Scalable test generators for high-speed datapath circuits
H Al-Asaad, JP Hayes, BT Murray
Journal of Electronic Testing 12 (1), 111-125, 1998
271998
Simulation-based approximate global fault collapsing
H Al-Assad, R Lee
Proc. International Conf. on VLSI, 72-77, 2002
242002
Logic design validation via simulation and automatic test pattern generation
H Al-Asaad, JP Hayes
Journal of Electronic Testing 16 (6), 575-589, 2000
182000
A new low power high performance flip-flop
A Sayed, H Al-Asaad
2006 49th IEEE International Midwest Symposium on Circuits and Systems 1 …, 2006
162006
ESIM: A multimodel design error and fault simulator for logic circuits
H Al-Asaad, JP Hayes
Proceedings 18th IEEE VLSI Test Symposium, 221-228, 2000
122000
Survey and Evaluation of Low-Power Full-Adder Cells.
A Sayed, H Al-Asaad
ESA/VLSI, 332-338, 2004
112004
Non-concurrent on-line testing via scan chains
H Al-Asaad, P Moore
2006 IEEE Autotestcon, 683-689, 2006
102006
Mutation-based validation of high-level microprocessor implementations
J Campos, H Al-Asaad
Proceedings. Ninth IEEE International High-Level Design Validation and Test …, 2004
102004
Lifetime validation of digital systems via fault modeling and test generation
HS Al-Asaad
University of Michigan, 1998
101998
Low-Power Flip-Flops: Survey, Comparative Evaluation, and a New Design
A Sayed, H Al-Asaad
International Journal of Engineering and Technology 3 (3), 279, 2011
82011
Efficient techniques for reducing error latency in on-line periodic built-in self-test
H Al-Asaad
IEEE instrumentation & measurement magazine 13 (4), 28-32, 2010
82010
Survey and Evaluation of Low-Power Flip-Flops.
A Sayed, H Al-Asaad
CDES, 77-83, 2006
82006
Concurrent design error simulation for high-level microprocessor implementations
J Campos, H Al-Asaad
Proceedings AUTOTESTCON 2004., 382-388, 2004
82004
A new statistical approach for glitch estimation in combinational circuits
A Sayed, H Al-Asaad
2007 IEEE International Symposium on Circuits and Systems, 1641-1644, 2007
72007
MVP: A mutation-based validation paradigm
J Campos, H Al-Asaad
Tenth IEEE International High-Level Design Validation and Test Workshop …, 2005
72005
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