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Heterogeneous 2.5 D integration on through silicon interposer
X Zhang, JK Lin, S Wickramanayaka, S Zhang, R Weerasekera, R Dutta, ...
Applied physics reviews 2 (2), 021308, 2015
An analytical capacitance model for through-silicon vias in floating silicon substrate
R Weerasekera, G Katti, R Dutta, S Zhang, KF Chang, J Zhou, ...
IEEE Transactions on Electron Devices 63 (3), 1182-1188, 2016
Fabrication and assembly of Cu-RDL-based 2.5-D low-cost through silicon interposer (LC–TSI)
G Katti, SW Ho, LH Yu, S Zhang, R Dutta, R Weerasekera, KF Chang, ...
IEEE Design & Test 32 (4), 23-31, 2015
High bandwidth interconnect design opportunities in 2.5 D Through-silicon interposer (TSI)
R Weerasekera, KF Chang, S Zhang, G Katti, HY Li, R Dutta, JR Cubillo
2016 IEEE 18th Electronics Packaging Technology Conference (EPTC), 241-244, 2016
Design and Development of High Density Fan-Out Wafer Level Package (HD-FOWLP) for Deep Neural Network (DNN) Chiplet Accelerators using Advanced Interface Bus (AIB)
MD Rotaru, W Tang, D Rahul, Z Zhang
2021 IEEE 71st Electronic Components and Technology Conference (ECTC), 1258-1263, 2021
An automatic chip-package co-design flow for multi-core neuromorphic computing SiPs
J Lan, VP Nambiar, R Sabapathy, R Dutta, CT Chong, MD Rotaru, KK Lin, ...
2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC), 77-80, 2020
Material removal rate prediction using the classification-regression approach
KL Lim, R Dutta
2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC), 172-175, 2020
Method and system for generating training data for a machine learning model for predicting performance in electronic design
R Dutta, R Salahuddin, KTC Chai
US Patent App. 17/296,657, 2022
Automated Design Flow for Millimeter-Wave Antenna in Fan-Out Wafer Level Packaging
S Wang, D Rahul, D Xie, LT Guan, F Che, Y Han, S Bhattacharya
2019 IEEE 21st Electronics Packaging Technology Conference (EPTC), 448-451, 2019
Monolithic integration of high capacitance (power/ground) and low
G Katti, Y Weiliang, R Weerasekera, CK Fai, R Dutta, SW Ho, HY Li, ...
2015 IEEE International Conference on Electron Devices and Solid-State …, 2015
NetFlex: A 22nm Multi-Chiplet Perception Accelerator in High-Density Fan-Out Wafer-Level Packaging
T Chou, W Tang, MD Rotaru, C Liu, R Dutta, SLP Siang, DHS Wee, ...
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022
Method and system for predicting performance in electronic design based on machine learning
R Salahuddin, R Dutta, KTC Chai, A James, CS Foo, Z Zeng, ...
US Patent App. 17/296,169, 2022
Prognostics and Health Management of Wafer Chemical-Mechanical Polishing System using Autoencoder
KL Lim, R Dutta
2021 IEEE International Conference on Prognostics and Health Management …, 2021
Learning of Multi-Dimensional Analog Circuits Through Generative Adversarial Network (GAN)
R Dutta, S Raju, A James, CJ Leo, YJ Jeon, B Unnikrishnan, CS Foo, ...
2019 32nd IEEE International System-on-Chip Conference (SOCC), 394-399, 2019
Heterogeneous system implementation using through-silicon interposer (TSI) technology
R Weerasekera, Z Songbai, R Dutta, G Katti, KF Chang, J Zhou, JK Lin, ...
2015 IEEE International Conference on Electron Devices and Solid-State …, 2015
Semi Supervised Learning of Multi-Dimensional Analog Circuits
BU Jeon, CS Foo, Z Zeng, KTC Chai, R Vijay
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