| Ultra-fast and high-reliability SOT-MRAM: From cache replacement to normally-off computing G Prenat, K Jabeur, P Vanhauwaert, G Di Pendina, F Oboril, R Bishnoi, ... IEEE Transactions on Multi-Scale Computing Systems 2 (1), 49-60, 2015 | 191 | 2015 |
| Spin orbit torque non-volatile flip-flop for high speed and low energy applications K Jabeur, G Di Pendina, F Bernard-Granger, G Prenat IEEE electron device letters 35 (3), 408-410, 2014 | 105 | 2014 |
| Beyond STT-MRAM, spin orbit torque RAM SOT-MRAM for high speed and high reliability applications G Prenat, K Jabeur, G Di Pendina, O Boulle, G Gaudin Spintronics-based Computing, 145-157, 2015 | 70 | 2015 |
| Non-volatile memory cell G Di Pendina, K Jabeur US Patent App. 14/446,044, 2015 | 45 | 2015 |
| Compact modeling of a magnetic tunnel junction based on spin orbit torque K Jabeur, G Di Pendina, G Prenat, LD Buda-Prejbeanu, B Dieny IEEE transactions on magnetics 50 (7), 1-8, 2014 | 41 | 2014 |
| Study of two writing schemes for a magnetic tunnel junction based on spin orbit torque K Jabeur, LD Buda-Prejbeanu, G Prenat, G Di Pendina International Journal of Electrical and Computer Engineering 7 (8), 1054-1059, 2013 | 30 | 2013 |
| Comparison of Verilog‐A compact modelling strategies for spintronic devices K Jabeur, F Bernard‐Granger, G Di Pendina, G Prenat, B Dieny Electronics letters 50 (19), 1353-1355, 2014 | 28 | 2014 |
| SPITT: A magnetic tunnel junction SPICE compact model for STT-MRAM F Bernard-Granger, B Dieny, R Fascio, K Jabeur Proceedings of the MOS-AK Workshop of the Design, Automation & Test in …, 2015 | 23 | 2015 |
| Compact model of a three-terminal MRAM device based on spin orbit torque switching K Jabeur, G Prenat, G Di Pendina, LD Buda-Prejbeanu, IL Prejbeanu, ... 2013 International Semiconductor Conference Dresden-Grenoble (ISCDG), 1-4, 2013 | 20 | 2013 |
| Spintronics-based computing G Prenat, K Jabeur, G Di Pendina, O Boulle, G Gaudin, W Zhao Spin orbit torque RAM SOT-MRAM for high speed and high reliability …, 2015 | 18 | 2015 |
| Ultra‐energy‐efficient CMOS/magnetic non‐volatile flip‐flop based on spin‐orbit torque device K Jabeur, G Di Pendina, G Prenat Electronics Letters 50 (8), 585-587, 2014 | 18 | 2014 |
| Fine-grain reconfigurable logic cells based on double-gate CNTFETs K Jabeur, N Yakymets, I O'Connor, S Le-Beux Proceedings of the 21st edition of the great lakes symposium on Great lakes …, 2011 | 16 | 2011 |
| Ambipolar double-gate FET binary-decision-diagram (Am-BDD) for reconfigurable logic cells K Jabeur, N Yakymets, I O'Connor, S Le Beux 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 162-168, 2011 | 14 | 2011 |
| Reducing transistor count in clocked standard cells with ambipolar double-gate FETs K Jabeur, D Navarro, I O'Connor, PE Gaillardon, MHB Jamaa, F Clermidy 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 47-52, 2010 | 14 | 2010 |
| Study of spin transfer torque (STT) and spin orbit torque (SOT) magnetic tunnel junctions (MTJS) at advanced CMOS technology nodes K Jabeur, G Pendina, G Prenat Electr. Electron. Eng. Int. J 6, 01-09, 2017 | 13 | 2017 |
| High performance 4: 1 multiplexer with ambipolar double-gate FETs K Jabeur, I O'Connor, N Yakymets, S Le Beux 2011 18th IEEE International Conference on Electronics, Circuits, and …, 2011 | 10 | 2011 |
| Ambipolar independent double gate FET (Am-IDGFET) for the design of compact logic structures K Jabeur, I O’Connor, S Le Beux IEEE Transactions on Nanotechnology 13 (6), 1063-1073, 2014 | 9 | 2014 |
| Ambipolar independent double gate FET logic I O'Connor, K Jabeur, S Le Beux, D Navarro Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale …, 2012 | 8 | 2012 |
| Tunable reference system with sense amplifier offset cancellation for magnetic random access memory K Jabeur, JK DeBrosse US Patent 10,741,232, 2020 | 6 | 2020 |
| Reducing system power consumption using check-pointing on nonvolatile embedded magnetic random access memories C Layer, L Becker, K Jabeur, S Claireux, B Dieny, G Prenat, GD Pendina, ... ACM Journal on Emerging Technologies in Computing Systems (JETC) 12 (4), 1-24, 2016 | 6 | 2016 |
