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Shaked Flur
Shaked Flur
Verified email at cl.cam.ac.uk - Homepage
Title
Cited by
Cited by
Year
Modelling the ARMv8 architecture, operationally: Concurrency and ISA
S Flur, KE Gray, C Pulte, S Sarkar, A Sezgin, L Maranget, W Deacon, ...
Proceedings of the 43rd Annual ACM SIGPLAN-SIGACT Symposium on Principles of …, 2016
1622016
Simplifying ARM concurrency: multicopy-atomic axiomatic and operational models for ARMv8
C Pulte, S Flur, W Deacon, J French, S Sarkar, P Sewell
Proceedings of the ACM on Programming Languages 2 (POPL), 1-29, 2017
1342017
ISA semantics for ARMv8-a, RISC-v, and CHERI-MIPS
A Armstrong, T Bauereiss, B Campbell, A Reid, KE Gray, R Norton-Wright, ...
Association for Computing Machinery (ACM), 2019
802019
Termination proofs for linear simple loops
HY Chen, S Flur, S Mukhopadhyay
International Journal on Software Tools for Technology Transfer 17 (1), 47-57, 2015
412015
Mixed-size concurrency: ARM, Power, C/C++ 11, and SC
S Flur, S Sarkar, C Pulte, K Nienhuis, L Maranget, KE Gray, A Sezgin, ...
ACM SIGPLAN Notices 52 (1), 429-442, 2017
402017
Repairing and mechanising the JavaScript relaxed memory model
C Watt, C Pulte, A Podkopaev, G Barbier, S Dolan, S Flur, ...
Proceedings of the 41st ACM SIGPLAN Conference on Programming Language …, 2020
152020
Formal verification of models using concurrent model-reduction and model-checking
E Arbel, S Flur, Z Nevo, M Shamis
US Patent 8,244,516, 2012
122012
ARMv8-A system semantics: instruction fetch in relaxed architectures
B Simner, S Flur, C Pulte, A Armstrong, J Pichon-Pharabod, L Maranget, ...
European Symposium on Programming, 626-655, 2020
102020
Assertion based verification of multiple-clock gals systems
R Dobkin, T Kapshitz, S Flur, R Ginosar
Proc. IFIP/IEEE Int. Conference on Very Large Scale Integration (VLSI-SoC), 2008
92008
Detailed models of instruction set architectures: From pseudocode to formal semantics
A Armstrong, T Bauereiss, B Campbell, S Flur, KE Gray, P Mundkur, ...
Proceedings of the 25th Automated Reasoning Workshop: Bridging the Gap …, 2018
82018
Formal verification of models using concurrent model-reduction and model-checking
E Arbel, S Flur, Z Nevo, M Shamis
US Patent 8,417,507, 2013
62013
The sail instruction-set semantics specification language
KE Gray, P Sewell, C Pulte, S Flur, R Norton-Wright
Technical report published by Cambridge University, 2017
52017
Model checking of liveness property in a phase abstracted model
JR Baumgartner, S Flur, Z Nevo, PJ Roessler
US Patent 8,627,273, 2014
52014
Towards making formal methods normal: meeting developers where they are
A Reid, L Church, S Flur, S de Haas, M Johnson, B Laurie
arXiv preprint arXiv:2010.16345, 2020
42020
The Sail instruction-set semantics specification language
A Armstrong, T Bauereiss, B Campbell, KE Gray, R Norton-Wright, C Pulte, ...
22021
Research data supporting “Mixed-size Concurrency: ARM, POWER, C/C++ 11, and SC”
S Flur, S Sarkar, C Pulte, K Nienhuis, L Maranget, KE Gray, A Sezgin, ...
University of Cambridge, 2016
2016
Detection of design redundancy
S Flur, Z Nevo
US Patent 8,554,522, 2013
2013
An Axiomatic Semantics for Instruction Fetching
B Simner, S Flur, C Pulte, A Armstrong, J Pichon-Pharabod, L Maranget, ...
Reduction Assistant: Model Reduction in Parallel with Model Checking
E Arbel, S Flur, Z Nevo, S Ruah, M Shamis
The Flat Operational Model
C PULTE, S FLUR, W DEACON, JON FRENCH, S SARKAR, P SEWELL
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Articles 1–20