| A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation K Tiri, I Verbauwhede Proceedings Design, Automation and Test in Europe Conference and Exhibition …, 2004 | 995 | 2004 |
| A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards K Tiri, M Akmal, I Verbauwhede Proceedings of the 28th European solid-state circuits conference, 403-406, 2002 | 800 | 2002 |
| Securing encryption algorithms against DPA at the logic level: Next generation smart card technology K Tiri, I Verbauwhede CHES 2779, 125-136, 2003 | 266 | 2003 |
| A digital design flow for secure integrated circuits K Tiri, I Verbauwhede IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006 | 211 | 2006 |
| AES-Based Security Coprocessor IC in 0.18-$ muhbox m $ CMOS With Resistance to Differential Power Analysis Side-Channel Attacks DD Hwang, K Tiri, A Hodjat, BC Lai, S Yang, P Schaumont, ... IEEE Journal of Solid-State Circuits 41 (4), 781-792, 2006 | 211 | 2006 |
| Prototype IC with WDDL and differential routing–DPA resistance assessment K Tiri, D Hwang, A Hodjat, BC Lai, S Yang, P Schaumont, I Verbauwhede Cryptographic Hardware and Embedded Systems–CHES 2005: 7th International …, 2005 | 202 | 2005 |
| Place and route for secure standard cell design K Tiri, I Verbauwhede Smart Card Research and Advanced Applications VI: IFIP 18th World Computer …, 2004 | 162 | 2004 |
| A VLSI design flow for secure side-channel attack resistant ICs K Tiri, I Verbauwhede Design, Automation and Test in Europe, 58-63, 2005 | 132 | 2005 |
| Securing embedded systems DD Hwang, P Schaumont, K Tiri, I Verbauwhede IEEE Security & Privacy 4 (02), 40-49, 2006 | 127 | 2006 |
| Masking and dual-rail logic don’t add up P Schaumont, K Tiri Cryptographic Hardware and Embedded Systems-CHES 2007: 9th International …, 2007 | 125 | 2007 |
| A side-channel leakage free coprocessor IC in 0.18 µm CMOS for Embedded AES-based Cryptographic and Biometric Processing K Tiri, D Hwang, A Hodjat, B Lai, S Yang, P Schaumont, I Verbauwhede Proceedings of the 42nd annual Design Automation Conference, 222-227, 2005 | 109 | 2005 |
| Simulation models for side-channel information leaks K Tiri, I Verbauwhede Proceedings of the 42nd annual Design Automation Conference, 228-233, 2005 | 96 | 2005 |
| Design method for constant power consumption of differential logic circuits K Tiri, I Verbauwhede Design, Automation and Test in Europe, 628-633, 2005 | 89 | 2005 |
| A 3.84 Gbits/s AES Crypto Coprocessor with Modes of Operation in a 0.18-μm CMOS Technology A Hodjat, DD Hwang, B Lai, K Tiri, I Verbauwhede Proceedings of the 15th ACM Great Lakes symposium on VLSI, 60-63, 2005 | 87 | 2005 |
| Side-channel attack pitfalls K Tiri Proceedings of the 44th annual Design Automation Conference, 15-20, 2007 | 75 | 2007 |
| An analytical model for time-driven cache attacks K Tiri, O Acıiçmez, M Neve, F Andersen Fast Software Encryption: 14th International Workshop, FSE 2007, Luxembourg …, 2007 | 75 | 2007 |
| Charge recycling sense amplifier based logic: securing low power security ICs against DPA [differential power analysis] K Tiri, I Verbauwhede Proceedings of the 30th European Solid-State Circuits Conference, 179-182, 2004 | 74 | 2004 |
| Changing the odds against masked logic K Tiri, P Schaumont Selected Areas in Cryptography: 13th International Workshop, SAC 2006 …, 2007 | 62 | 2007 |
| Dynamic and differential CMOS logic with signal-independent power consumption to withstand differential power analysis IM Verbauwhede, KJV Tiri US Patent 7,417,468, 2008 | 60 | 2008 |
| Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate M Badaroglu, G Van der Plas, P Wambacq, L Balasubramanian, K Tiri, ... IEEE journal of solid-state circuits 39 (7), 1119-1130, 2004 | 49 | 2004 |
