| An exact algorithm for wirelength optimal placements in VLSI design J Funke, S Hougardy, J Schneider Integration 52, 355-366, 2016 | 37 | 2016 |
| Automatic cell layout in the 7nm era P Cremer, S Hougardy, J Schneider, J Silvanus Proceedings of the 2017 ACM on International Symposium on Physical Design …, 2017 | 29 | 2017 |
| BonnCell: Automatic layout of leaf cells S Hougardy, T Nieberg, J Schneider 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 453-460, 2013 | 17 | 2013 |
| Rectangle packing with additional restrictions J Maßberg, J Schneider Theoretical computer science 412 (50), 6948-6958, 2011 | 10 | 2011 |
| Rectangle packing with additional restrictions J Maßberg, J Schneider | 10 | 2010 |
| Transistor-Level Layout of Integrated Circuits J Schneider Universitäts-und Landesbibliothek Bonn, 2014 | 9 | 2014 |
| Macro Placement in VLSI Design J Schneider Research Institute for Discrete Mathematics, University of Bonn, 2009 | 5 | 2009 |
| Largest empty square queries in rectilinear polygons M Gester, N Hähnle, J Schneider Computational Science and Its Applications--ICCSA 2015: 15th International …, 2015 | 4 | 2015 |
| Wirelength optimal rectangle packings J Funke, S Hougardy, J Schneider Proceedings of the Fourth International Workshop on Bin Packing and …, 2012 | 4 | 2012 |
| Combinatorial Optimization S Held, J Vygen, P Cremer | 2 | 2015 |
| Automatic Cell Layout in the 7nm Era P Van Cleeff, S Hougardy, J Silvanus, J Schneider Forschungsinstitut für Diskrete Mathematik Rheinische Friedrich-Wilhelms …, 2017 | | 2017 |
| Wirelength Optimal Results for the MCNC Block Packing Instances J Funke, S Hougardy, J Schneider Forschungsinst. für Diskrete Mathematik, 2011 | | 2011 |
