| A 1.7 mW 11b 250 MS/s 2-times interleaved fully dynamic pipelined SAR ADC in 40 nm digital CMOS B Verbruggen, M Iriguchi, J Craninckx IEEE Journal of Solid-State Circuits 47 (12), 2880-2887, 2012 | 209 | 2012 |
| A 40 nm CMOS 0.4–6 GHz receiver resilient to out-of-band blockers J Borremans, G Mandal, V Giannini, B Debaillie, M Ingels, T Sano, ... IEEE Journal of Solid-State Circuits 46 (7), 1659-1671, 2011 | 194 | 2011 |
| A 0.9 V 0.4–6 GHz harmonic recombination SDR receiver in 28 nm CMOS with HR3/HR5 and IIP2 calibration B van Liempd, J Borremans, E Martens, S Cha, H Suys, B Verbruggen, ... IEEE Journal of Solid-State Circuits 49 (8), 1815-1826, 2014 | 119 | 2014 |
| A 150 MS/s 133W 7 bit ADC in 90 nm Digital CMOS G Van der Plas, B Verbruggen IEEE Journal of Solid-State Circuits 43 (12), 2631-2640, 2008 | 108 | 2008 |
| A 70 db sndr 200 ms/s 2.3 mw dynamic pipelined sar adc in 28nm digital cmos B Verbruggen, K Deguchi, B Malki, J Craninckx 2014 Symposium on VLSI Circuits Digest of Technical Papers, 1-2, 2014 | 107 | 2014 |
| A 2.2 mW 5b 1.75 GS/s folding flash ADC in 90nm digital CMOS B Verbruggen, J Craninckx, M Kuijk, P Wambacq, G Van der Plas 2008 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2008 | 101 | 2008 |
| A 2.2 mW 1.75 GS/s 5 bit folding flash ADC in 90 nm digital CMOS B Verbruggen, J Craninckx, M Kuijk, P Wambacq, G Van der Plas IEEE Journal of Solid-State Circuits 44 (3), 874-882, 2009 | 94 | 2009 |
| A 40nm CMOS highly linear 0.4-to-6GHz receiver resilient to 0dBm out-of-band blockers J Borremans, G Mandal, V Giannini, T Sano, M Ingels, B Verbruggen, ... 2011 IEEE International Solid-State Circuits Conference, 62-64, 2011 | 87 | 2011 |
| A 2.4 GHz Low-Power Sixth-Order RF Bandpass Converter in CMOS J Ryckaert, J Borremans, B Verbruggen, L Bos, C Armiento, J Craninckx, ... IEEE Journal of Solid-State Circuits 44 (11), 2873-2880, 2009 | 85 | 2009 |
| A 150MS/s 133μW 7b ADC in 90nm digital CMOS using a comparator-based asynchronous binary-search sub-ADC G Van Der Plas, B Verbruggen 2008 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2008 | 85 | 2008 |
| 16.1 A 13b 4GS/s digitally assisted dynamic 3-stage asynchronous pipelined-SAR ADC B Vaz, A Lynam, B Verbruggen, A Laraba, C Mesadri, A Boumaalif, ... 2017 IEEE International Solid-State Circuits Conference (ISSCC), 276-277, 2017 | 81 | 2017 |
| A 70 dB DR 10 b 0-to-80 MS/s current-integrating SAR ADC with adaptive dynamic range B Malki, T Yamamoto, B Verbruggen, P Wambacq, J Craninckx IEEE Journal of Solid-State Circuits 49 (5), 1173-1183, 2014 | 80 | 2014 |
| A 2.1 mW 11b 410 MS/s dynamic pipelined SAR ADC with background calibration in 28nm digital CMOS B Verbruggen, M Iriguchi, M de la Guia Solaz, G Glorieux, K Deguchi, ... 2013 Symposium on VLSI Circuits, C268-C269, 2013 | 77 | 2013 |
| A 2.6 mW 6b 2.2 GS/s 4-times interleaved fully dynamic pipelined ADC in 40nm digital CMOS B Verbruggen, J Craninckx, M Kuijk, P Wambacq, G Van der Plas 2010 IEEE International Solid-State Circuits Conference-(ISSCC), 296-297, 2010 | 76 | 2010 |
| A 7.4-to-14GHz PLL with 54fsrms jitter in 16nm FinFET for integrated RF-data-converter SoCs D Turker, A Bekele, P Upadhyaya, B Verbruggen, Y Cao, S Ma, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 378-380, 2018 | 73 | 2018 |
| Digitally modulated CMOS polar transmitters for highly-efficient mm-wave wireless communication K Khalaf, V Vidojkovic, K Vaesen, M Libois, G Mangraviti, V Szortyka, C Li, ... IEEE Journal of Solid-State Circuits 51 (7), 1579-1592, 2016 | 62 | 2016 |
| A 2.6 mW 6 bit 2.2 GS/s fully dynamic pipeline ADC in 40 nm digital CMOS B Verbruggen, J Craninckx, M Kuijk, P Wambacq, G Van der Plas IEEE journal of solid-state circuits 45 (10), 2080-2090, 2010 | 60 | 2010 |
| The potential of FinFETs for analog and RF circuit applications P Wambacq, B Verbruggen, K Scheir, J Borremans, M Dehan, D Linten, ... IEEE Transactions on Circuits and Systems I: Regular Papers 54 (11), 2541-2551, 2007 | 59 | 2007 |
| A 7.6 mW 1.75 GS/s 5 bit flash A/D converter in 90 nm digital CMOS B Verbruggen, P Wambacq, M Kuijk, G Van der Plas 2008 IEEE Symposium on VLSI Circuits, 14-15, 2008 | 52 | 2008 |
| 16.3 A 330mW 14b 6.8 GS/s dual-mode RF DAC in 16nm FinFET achieving− 70.8 dBc ACPR in a 20MHz channel at 5.2 GHz C Erdmann, E Cullen, D Brouard, R Pelliconi, B Verbruggen, J Mcgrath, ... 2017 IEEE International Solid-State Circuits Conference (ISSCC), 280-281, 2017 | 48 | 2017 |
