| Defect injection, fault modeling and test algorithm generation methodology for STT-MRAM SM Nair, R Bishnoi, MB Tahoori, G Tshagharyan, H Grigoryan, ... 2018 IEEE International Test Conference (ITC), 1-10, 2018 | 34 | 2018 |
| A spintronics memory PUF for resilience against cloning counterfeit SB Dodo, R Bishnoi, SM Nair, MB Tahoori IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (11 …, 2019 | 31 | 2019 |
| VAET-STT: Variation aware STT-MRAM analysis and design space exploration tool SM Nair, R Bishnoi, MS Golanbari, F Oboril, F Hameed, MB Tahoori IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 21 | 2017 |
| Process variation and temperature aware adaptive scrubbing for retention failures in STT-MRAM N Sayed, SM Nair, R Bishnoi, MB Tahoori 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), 203-208, 2018 | 19 | 2018 |
| Defect characterization and test generation for spintronic-based compute-in-memory SM Nair, C Münch, MB Tahoori 2020 IEEE European Test Symposium (ETS), 1-6, 2020 | 18 | 2020 |
| VAET-STT: A variation aware estimator tool for STT-MRAM based memories SM Nair, R Bishnoi, MS Golanbari, F Oboril, MB Tahoori Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017 | 15 | 2017 |
| Special session–emerging memristor based memory and CIM architecture: Test, repair and yield analysis R Bishnoi, L Wu, M Fieback, C Münch, SM Nair, M Tahoori, Y Wang, H Li, ... 2020 IEEE 38th VLSI Test Symposium (VTS), 1-10, 2020 | 12 | 2020 |
| A comprehensive framework for parametric failure modeling and yield analysis of STT-MRAM SM Nair, R Bishnoi, MB Tahoori IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (7 …, 2019 | 12 | 2019 |
| Variation-aware physics-based electromigration modeling and experimental calibration for VLSI interconnects SM Nair, R Bishnoi, MB Tahoori, H Zahedmanesh, K Croes, K Garello, ... 2019 IEEE International Reliability Physics Symposium (IRPS), 1-6, 2019 | 9 | 2019 |
| Dynamic faults based hardware trojan design in stt-mram SM Nair, R Bishnoi, A Vijayan, MB Tahoori 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 933-938, 2020 | 8 | 2020 |
| Parametric failure modeling and yield analysis for STT-MRAM SM Nair, R Bishnoi, MB Tahoori 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 265-268, 2018 | 8 | 2018 |
| Workload-aware electromigration analysis in emerging spintronic memory arrays SM Nair, M Mayahinia, MB Tahoori, M Perumkunnil, H Zahedmanesh, ... IEEE Transactions on Device and Materials Reliability 21 (2), 258-266, 2021 | 7 | 2021 |
| Mitigating read failures in stt-mram SM Nair, R Bishnoi, MB Tahoori 2020 IEEE 38th VLSI Test Symposium (VTS), 1-6, 2020 | 7 | 2020 |
| Physics based modeling of bimodal electromigration failure distributions and variation analysis for VLSI interconnects SM Nair, R Bishnoi, MB Tahoori, H Zahedmanesh, K Croes, K Garello, ... 2020 IEEE International Reliability Physics Symposium (IRPS), 1-5, 2020 | 5 | 2020 |
| Using multifunctional standardized stack as universal spintronic technology for IoT M Tahoori, SM Nair, R Bishnoi, S Senni, J Mohdad, F Mailly, L Torres, ... 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 931-936, 2018 | 5 | 2018 |
| GREAT: heteroGeneous integRated magnetic tEchnology using multifunctional standardized sTack M Tahoori, SM Nair, R Bishnoi, S Senni, J Mohdad, F Mailly, L Torres, ... 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 344-349, 2017 | 5 | 2017 |
| Variation analysis, fault modeling and yield improvement of emerging spintronic memories SM Nair KIT-Bibliothek, 2020 | 3 | 2020 |
| Variation-aware fault modeling and test generation for STT-MRAM SM Nair, R Bishnoi, MB Tahoori, H Grigoryan, G Tshagharyan 2019 IEEE 25th International Symposium on On-Line Testing and Robust System …, 2019 | 3 | 2019 |
| A universal spintronic technology based on multifunctional standardized stack M Tahoori, SM Nair, R Bishnoi, L Torres, S Senni, G Patrigeon, P Benoit, ... 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 394-399, 2020 | 1 | 2020 |
| High-Performance Radiation-Hardened Spintronic Retention Latch and Flip-Flop for Highly Reliable Processors SM Nair, M Mayahinia, MB Tahoori, M Perumkunnil, H Zahedmanesh, ... Ieee Transactions On Device And Materials Reliability 21 (2), 258-266, 2021 | | 2021 |
Mehdi B. TahooriProfessor of Computer Science, Karlsruhe Institute of Technology, GermanyBestätigte E-Mail-Adresse bei kit.edu
