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Jeongsup Lee
Jeongsup Lee
Apple Inc.
Verified email at umich.edu
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Cited by
Year
Toward an open-source digital flow: First learnings from the openroad project
T Ajayi, VA Chhabria, M Fogaça, S Hashemi, A Hosny, AB Kahng, M Kim, ...
Proceedings of the 56th Annual Design Automation Conference 2019, 1-4, 2019
1432019
Capacitor array structure and switch control for energy-efficient SAR analog-to-digital converters
JS Lee, IC Park
2008 IEEE International Symposium on Circuits and Systems (ISCAS), 236-239, 2008
552008
A Self-Tuning IoT Processor Using Leakage-Ratio Measurement for Energy-Optimal Operation
J Lee, Y Zhang, Q Dong, W Lim, M Saligane, Y Kim, S Jeong, J Lim, ...
IEEE Journal of Solid-State Circuits 55 (1), 87-97, 2019
452019
A 0.87 W transceiver IC for 100 gigabit Ethernet in 40 nm CMOS
H Won, T Yoon, J Han, JY Lee, JH Yoon, T Kim, JS Lee, S Lee, K Han, ...
IEEE Journal of Solid-State Circuits 50 (2), 399-413, 2014
342014
19.2 A 6.4 pJ/cycle self-tuning cortex-M0 IoT processor based on leakage-ratio measurement for energy-optimal operation across wide-range PVT variation
J Lee, Y Zhang, Q Dong, W Lim, M Saligane, Y Kim, S Jeong, J Lim, ...
2019 IEEE International Solid-State Circuits Conference-(ISSCC), 314-315, 2019
212019
An automatic loop gain control algorithm for bang-bang CDRs
SW Kwon, JY Lee, J Lee, K Han, T Kim, S Lee, JS Lee, T Yoon, H Won, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 62 (12), 2817-2828, 2015
162015
A Noise-Efficient Neural Recording Amplifier Using Discrete-Time Parametric Amplification
T Jang, J Lim, K Choo, S Nason, J Lee, S Oh, C Chestek, D Sylvester, ...
IEEE Solid-State Circuits Letters 1 (11), 203-206, 2018
122018
A 2.2 NEF neural-recording amplifier using discrete-time parametric amplification
T Jang, J Lim, K Choo, S Nason, J Lee, S Oh, S Jeong, C Chestek, ...
2018 IEEE Symposium on VLSI Circuits, 237-238, 2018
82018
A Power-and-Area EfficientGb/s Bootstrap Transceiver in 40 nm CMOS for Referenceless and Lane-Independent Operation
JY Lee, K Han, T Yoon, T Kim, SE Lee, JS Lee, J Park, HM Bae
IEEE Journal of Solid-State Circuits 51 (10), 2475-2484, 2016
82016
An Adaptive Body-Biaslna SoC Using in Situ Slack Monitoring for Runtime Replica Calibration
M Saligane, J Lee, Q Dong, M Yasuda, K Kumeno, F Ohno, S Miyoshi, ...
2018 IEEE Symposium on VLSI Circuits, 63-64, 2018
72018
A 0.3-V to 1.8–3.3-V Leakage-Biased Synchronous Level Converter for ULP SoCs
J Lee, M Saligane, D Blaauw, D Sylvester
IEEE Solid-State Circuits Letters 3, 130-133, 2020
62020
An ultra-wide program, 122pJ/bit flash memory using charge recycling
S Jeloka, J Lee, Z Li, J Shah, Q Dong, K Yang, D Sylvester, D Blaauw
2017 Symposium on VLSI Circuits, C196-C197, 2017
42017
AProcessor Layer for mm-Scale Die-Stacked Sensing Platforms Featuring Ultra-Low Power Sleep Mode at 125°C
J Lee, Y Kim, M Cho, M Yasuda, S Miyoshi, M Kawaminami, D Blaauw, ...
2020 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1-4, 2020
22020
Level converter circuitry
J Lee, M Saligane, DT Blaauw, DMC Sylvester
US Patent 10,326,449, 2019
22019
A 100-GbE reverse gearbox IC in 40nm CMOS for supporting legacy 10-and 40-GbE standards
T Yoon, JY Lee, K Han, J Lee, S Lee, T Kim, H Won, J Park, HM Bae
2015 Symposium on VLSI Circuits (VLSI Circuits), C212-C213, 2015
22015
Design Techniques of Integrated Power Management Circuits for Low Power Edge Devices
L Xu, J Lee, M Saligane, D Blaauw, D Sylvester
2021 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2021
12021
A 103.125-Gb/s reverse gearbox IC in 40-nm CMOS for supporting legacy 10-and 40-GbE links
T Yoon, JY Lee, J Lee, K Han, JS Lee, S Lee, T Kim, J Han, H Won, J Park, ...
IEEE Journal of Solid-State Circuits 52 (3), 688-703, 2017
12017
A fully integrated, automatically generated DC-DC converter maintaining> 75% efficiency from 398 K down to 23 K across wide load ranges in 12 nm FinFET
A Li, J Lee, P Mukim, BD Hoskins, P Shrestha, D Wentzloff, D Blaauw, ...
IEEE Solid-State Circuits Letters, 2024
2024
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