| Architecture and CAD for deep-submicron FPGAs V Betz, J Rose, A Marquardt Springer Science & Business Media, 1999 | 1642* | 1999 |
| Measuring the gap between FPGAs and ASICs I Kuon, J Rose IEEE Transactions on computer-aided design of integrated circuits and …, 2007 | 1567 | 2007 |
| VPR: A new packing, placement and routing tool for FPGA research V Betz, J Rose International Workshop on Field Programmable Logic and Applications, 213-222, 1997 | 1418 | 1997 |
| Field-Programmable Gate Arrays S Brown, R Francis, J Rose, Z Vranesic Kluwer/Springer, ISBN 978-0-7923-9248-4, 1992 | 1195 | 1992 |
| FPGA and CPLD architectures: A tutorial S Brown, J Rose IEEE design & test of computers 13 (2), 42-57, 1996 | 790* | 1996 |
| The effect of LUT and cluster size on deep-submicron FPGA performance and density E Ahmed, J Rose IEEE Transactions on Very Large Scale Integration (VLSI) Systems 12 (3), 288-298, 2004 | 748 | 2004 |
| FPGA architecture: Survey and challenges I Kuon, R Tessier, J Rose Now Publishers Inc, 2008 | 685 | 2008 |
| Architecture of field-programmable gate arrays J Rose, A El Gamal, A Sangiovanni-Vincentelli Proceedings of the IEEE 81 (7), 1013-1029, 1993 | 471 | 1993 |
| Architecture of field-programmable gate arrays: The effect of logic block functionality on area efficiency J Rose, RJ Francis, D Lewis, P Chow IEEE Journal of Solid-State Circuits 25 (5), 1217-1225, 1990 | 424 | 1990 |
| VTR 7.0: Next generation architecture and CAD system for FPGAs J Luu, J Goeders, M Wainberg, A Somerville, T Yu, K Nasartschuk, M Nasr, ... ACM Transactions on Reconfigurable Technology and Systems (TRETS) 7 (2), 1-30, 2014 | 342 | 2014 |
| Chortle-crf: Fast technology mapping for lookup table-based FPGAs R Francis, J Rose, Z Vranesic Proceedings of the 28th ACM/IEEE design automation conference, 227-233, 1991 | 341 | 1991 |
| Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density A Marquardt, V Betz, J Rose Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field …, 1999 | 340 | 1999 |
| Timing-driven placement for FPGAs A Marquardt, V Betz, J Rose Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field …, 2000 | 323 | 2000 |
| VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling J Luu, I Kuon, P Jamieson, T Campbell, A Ye, WM Fang, K Kent, J Rose ACM Transactions on Reconfigurable Technology and Systems (TRETS) 4 (4), 1-23, 2011 | 312 | 2011 |
| The VTR project: architecture and CAD for FPGAs from verilog to routing J Rose, J Luu, CW Yu, O Densmore, J Goeders, A Somerville, KB Kent, ... Proceedings of the ACM/SIGDA international symposium on Field Programmable …, 2012 | 311 | 2012 |
| Flexibility of interconnection structures for field-programmable gate arrays J Rose, S Brown IEEE Journal of Solid-State Circuits 26 (3), 277-282, 1991 | 291 | 1991 |
| Architectures and algorithms for field-programmable gate arrays with embedded memory SJE Wilton PhD thesis, University of Toronto, 1997 | 233 | 1997 |
| A detailed router for field-programmable gate arrays S Brown, J Rose, ZG Vranesic IEEE transactions on computer-aided design of integrated circuits and …, 1992 | 231 | 1992 |
| The Stratix II logic and routing architecture D Lewis, E Ahmed, G Baeckler, V Betz, M Bourgeault, D Cashman, ... Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field …, 2005 | 227 | 2005 |
| FPGA routing architecture: Segmentation and buffering to optimize speed and density V Betz, J Rose Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field …, 1999 | 224 | 1999 |
Vaughn BetzUniversity of TorontoVerified email at eecg.utoronto.ca
