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Luis Lastras
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Phase change memory technology
GW Burr, MJ Breitwisch, M Franceschini, D Garetto, K Gopalakrishnan, ...
Journal of Vacuum Science & Technology B, Nanotechnology and …, 2010
10582010
Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling
MK Qureshi, J Karidis, M Franceschini, V Srinivasan, L Lastras, B Abali
2009 42nd Annual IEEE/ACM international symposium on microarchitecture …, 2009
8782009
Improving read performance of phase change memories via write cancellation and write pausing
MK Qureshi, MM Franceschini, LA Lastras-Montano
HPCA-16 2010 The Sixteenth International Symposium on High-Performance …, 2010
3642010
Morphable memory system: a robust architecture for exploiting multi-level phase change memories
MK Qureshi, MM Franceschini, LA Lastras-Montano, JP Karidis
Proceedings of the 37th annual international symposium on Computer …, 2010
2372010
PreSET: Improving performance of phase change memories by exploiting asymmetry in write times
MK Qureshi, MM Franceschini, A Jagmohan, LA Lastras
ACM SIGARCH Computer Architecture News 40 (3), 380-391, 2012
1932012
Resistive memory devices having a not-and (NAND) structure
MJ Breitwisch, GS Ditlow, MM Franceschini, LA Lastras-Montano, ...
US Patent 8,107,276, 2012
1682012
High availability memory system
JA O'connor, KC Gower, LA Lastras-Montano, WE Maule
US Patent 8,086,783, 2011
1392011
Systems and methods for error detection in a memory system
LA Lastras-Montano
US Patent 7,949,931, 2011
1382011
Heterogeneous recovery in a redundant memory system
KC Gower, LA Lastras-Montano, PJ Meaney, VK Papazova, E Stephens
US Patent 8,775,858, 2014
1362014
Practical and secure pcm systems by online detection of malicious write streams
MK Qureshi, A Seznec, LA Lastras, MM Franceschini
2011 IEEE 17th International symposium on high performance computer …, 2011
1082011
System and method for providing a high fault tolerant memory system
LA Lastras-Montano, JA O'connor, LC Alves, WJ Clarke, TJ Dell, ...
US Patent 8,041,989, 2011
932011
System and method for error correction and detection in a memory system
JA O'connor, LA Lastras-Montano, LC Alves, WJ Clarke, TJ Dell, ...
US Patent 8,041,990, 2011
892011
Bus attached compressed random access memory
B Abali, JP Karidis, LA Lastras-Montano
US Patent App. 12/098,900, 2009
812009
Prediction based priority scheduling
DM Daly, PA Franaszek, LA Lastras-Montano
US Patent 8,185,899, 2012
772012
Iterative write pausing techniques to improve read latency of memory systems
MM Franceschini, LA Lastras-Montano, MK Qureshi, V Srinivasan
US Patent 8,004,884, 2011
772011
Adaptive endurance coding of non-volatile memories
MM Franceschini, A Jagmohan, JP Karidis, LA Lastras-Montano
US Patent 8,341,501, 2012
76*2012
All sources are nearly successively refinable
L Lastras, T Berger
IEEE Transactions on Information Theory 47 (3), 918-926, 2001
732001
Reliable memories with subline accesses
J Han, LA Lastras-Montano
2007 IEEE International Symposium on Information Theory, 2531-2535, 2007
722007
System and method for providing DRAM device-level repair via address remappings external to the device
LA Lastras-Montano, DL Anand, JH Dreibelbis, CA Kilmer, WE Maule, ...
US Patent 7,984,329, 2011
692011
Cognitive operations based on empirically constructed knowledge graphs
LA Lastras-Montano, V Misra, LB Soares
US Patent 10,664,757, 2020
602020
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