Folgen
Eleonora Testa
Eleonora Testa
Bestätigte E-Mail-Adresse bei synopsys.com
Titel
Zitiert von
Zitiert von
Jahr
The EPFL logic synthesis libraries
M Soeken, H Riener, W Haaswijk, E Testa, B Schmitt, G Meuli, F Mozafari, ...
arXiv preprint arXiv:1805.05121, 2018
1172018
Reducing the multiplicative complexity in logic networks for cryptography and security applications
E Testa, M Soeken, L Amarù, G De Micheli
Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019
472019
Logic synthesis for established and emerging computing
E Testa, M Soeken, LG Amar, G De Micheli
Proceedings of the IEEE 107 (1), 165-184, 2018
422018
Scalable generic logic synthesis: One approach to rule them all
H Riener, E Testa, W Haaswijk, A Mishchenko, L Amarù, G De Micheli, ...
Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019
392019
Practical exact synthesis
M Soeken, W Haaswijk, E Testa, A Mishchenko, LG Amarù, RK Brayton, ...
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 309-314, 2018
332018
Inversion optimization in majority-inverter graphs
E Testa, M Soeken, O Zografos, L Amaru, P Raghavan, R Lauwereins, ...
2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH …, 2016
292016
Algebraic and Boolean optimization methods for AQFP superconducting circuits
E Testa, SY Lee, H Riener, G De Micheli
Proceedings of the 26th Asia and South Pacific Design Automation Conference …, 2021
282021
Size optimization of MIGs with an application to QCA and STMG technologies
H Riener, E Testa, L Amaru, M Soeken, G De Micheli
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale …, 2018
282018
A logic synthesis toolbox for reducing the multiplicative complexity in logic networks
E Testa, M Soeken, H Riener, L Amaru, G De Micheli
2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 568-573, 2020
262020
Inverter propagation and fan-out constraints for beyond-CMOS majority-based technologies
E Testa, O Zografos, M Soeken, A Vaysset, M Manfrini, R Lauwereins, ...
2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 164-169, 2017
222017
Three-input gates for logic synthesis
DS Marakkalage, E Testa, H Riener, A Mishchenko, M Soeken, ...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020
212020
Wave pipelining for majority-based beyond-CMOS technologies
O Zografos, A De Meester, E Testa, M Soeken, PE Gaillardon, ...
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017
212017
Classifying functions with exact synthesis
W Haaswijk, E Testa, M Soeken, G De Micheli
2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL), 272-277, 2017
182017
Mapping monotone Boolean functions into majority
E Testa, M Soeken, LG Amarù, W Haaswijk, G De Micheli
IEEE Transactions on Computers 68 (5), 791-797, 2018
172018
Majority logic synthesis
L Amarù, E Testa, M Couceiro, O Zografos, G De Micheli, M Soeken
2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-6, 2018
162018
Extending boolean methods for scalable logic synthesis
E Testa, L Amaru, M Soeken, A Mishchenko, P Vuillod, PE Gaillardon, ...
IEEE Access 8, 226828-226844, 2020
122020
Scalable Boolean methods in a modern synthesis flow
E Testa, L Amarú, M Soeken, A Mishchenko, P Vuillod, J Luo, C Casares, ...
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2019
122019
SAT-sweeping enhanced for logic synthesis
L Amarú, F Marranghello, E Testa, C Casares, V Possani, J Luo, P Vuillod, ...
2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020
102020
Exact synthesis for logic synthesis applications with complex constraints
E Testa, M Soeken, O Zografos, F Catthoor, G De Micheli
Proceedings of the 26th International Workshop on Logic & Synthesis (IWLS), 2017
102017
LUT-based optimization for ASIC design flow
L Amarú, V Possani, E Testa, F Marranghello, C Casares, J Luo, P Vuillod, ...
2021 58th ACM/IEEE Design Automation Conference (DAC), 871-876, 2021
92021
Das System kann den Vorgang jetzt nicht ausführen. Versuchen Sie es später erneut.
Artikel 1–20