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Martin Schmatz
Martin Schmatz
Researcher @ IBM
Bestätigte E-Mail-Adresse bei zurich.ibm.com
Titel
Zitiert von
Zitiert von
Jahr
A 3.1 mW 8b 1.2 GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32 nm digital SOI CMOS
L Kull, T Toifl, M Schmatz, PA Francese, C Menolfi, M Braendli, M Kossel, ...
IEEE Journal of Solid-State Circuits 48 (12), 3049-3058, 2013
3082013
22.1 a 90gs/s 8b 667mw 64× interleaved sar adc in 32nm digital soi cmos
L Kull, T Toifl, M Schmatz, PA Francese, C Menolfi, M Braendli, M Kossel, ...
2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014
2092014
A low-power 20-GHz 52-dB/spl Omega/transimpedance amplifier in 80-nm CMOS
C Kromer, G Sialm, T Morf, ML Schmatz, F Ellinger, D Erni, H Jackel
IEEE Journal of Solid-State Circuits 39 (6), 885-894, 2004
2002004
A 100-mW 4/spl times/10 Gb/s transceiver in 80-nm CMOS for high-density optical interconnects
C Kromer, G Sialm, C Berger, T Morf, ML Schmatz, F Ellinger, D Erni, ...
IEEE Journal of Solid-State Circuits 40 (12), 2667-2679, 2005
1692005
A T-Coil-Enhanced 8.5 Gb/s High-Swing SST Transmitter in 65 nm Bulk CMOS With 16 dB Return Loss Over 10 GHz Bandwidth
M Kossel, C Menolfi, J Weiss, P Buchmann, G Von Bueren, L Rodoni, ...
IEEE Journal of Solid-State Circuits 43 (12), 2905-2920, 2008
1532008
A 22-Gb/s PAM-4 receiver in 90-nm CMOS SOI technology
T Toifl, C Menolfi, M Ruegg, R Reutemann, P Buchmann, M Kossel, ...
IEEE Journal of Solid-State Circuits 41 (4), 954-965, 2006
1232006
High-density optical interconnects within large-scale systems
C Berger, MA Kossel, C Menolfi, T Morf, T Toifl, ML Schmatz
VCSELs and Optical Interconnects 4942, 222-235, 2003
1112003
A 25-Gb/s CDR in 90-nm CMOS for high-density interconnects
C Kromer, G Sialm, C Menolfi, M Schmatz, F Ellinger, H Jackel
IEEE Journal of Solid-State Circuits 41 (12), 2921-2929, 2006
962006
A 16Gb/s source-series terminated transmitter in 65nm CMOS SOI
C Menolfi, T Toifl, P Buchmann, M Kossel, T Morf, J Weiss, M Schmatz
2007 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2007
942007
60 GHz VCO with wideband tuning range fabricated on VLSI SOI CMOS technology
F Ellinger, T Morf, G Buren, C Kromer, G Sialm, L Rodoni, M Schmatz, ...
2004 IEEE MTT-S International Microwave Symposium Digest (IEEE Cat. No …, 2004
922004
30-40-GHz drain-pumped passive-mixer MMIC fabricated on VLSI SOI CMOS technology
F Ellinger, LC Rodoni, G Sialm, C Kromer, G von Buren, ML Schmatz, ...
IEEE transactions on microwave theory and techniques 52 (5), 1382-1391, 2004
842004
A 0.94-ps-RMS-jitter 0.016-mm/sup 2/2.5-GHz multiphase generator PLL with 360/spl deg/digitally programmable phase shift for 10-Gb/s serial links
T Toifl, C Menolfi, P Buchmann, M Kossel, T Morf, R Reutemann, ...
IEEE journal of solid-state circuits 40 (12), 2700-2712, 2005
792005
Power-on initialization and test for a cascade interconnect memory system
PL Buchmann, FD Ferraiolo, KC Gower, RJ Reese, EE Retter, ...
US Patent 8,139,430, 2012
752012
A 5.75 to 44 Gb/s quarter rate CDR with data rate selection in 90 nm bulk CMOS
L Rodoni, G von Buren, A Huber, M Schmatz, H Jackel
IEEE Journal of Solid-State Circuits 44 (7), 1927-1941, 2009
722009
Implementation of low-power 6–8 b 30–90 GS/s time-interleaved ADCs with optimized input bandwidth in 32 nm CMOS
L Kull, J Pliva, T Toifl, M Schmatz, PA Francese, C Menolfi, M Brändli, ...
IEEE Journal of Solid-State Circuits 51 (3), 636-648, 2016
662016
Method for determining jitter of a signal in a serial link and high speed serial link
HC Cranford Jr, MA Kossel, VR Norman, ML Schmatz
US Patent 7,295,604, 2007
612007
Methods and arrangements for link power reduction
HC Cranford Jr, GJ Nicholls, VR Norman, ML Schmatz, KD Selander, ...
US Patent 7,397,876, 2008
592008
A 35mW8 b 8.8 GS/s SAR ADC with low-power capacitive reference buffers in 32nm Digital SOI CMOS
L Kull, T Toifl, M Schmatz, PA Francese, C Menolfi, M Braendli, M Kossel, ...
2013 Symposium on VLSI Circuits, C260-C261, 2013
552013
Off-line gain calibration in a time-interleaved analog-to-digital converter
AR Bonaccio, FR Keyser III, ML Schmatz, BT Voegli
US Patent 8,587,464, 2013
542013
Receiver for clock and data recovery and method for calibrating sampling phases in a receiver for clock and data recovery
HC Cranford Jr, VR Norman, M Schmatz
US Patent 7,149,269, 2006
512006
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