| Rsyn: An extensible physical synthesis framework G Flach, M Fogaça, J Monteiro, M Johann, R Reis Proceedings of the 2017 ACM on International Symposium on Physical Design, 33-40, 2017 | 32 | 2017 |
| A1CSA: An energy-efficient fast adder architecture for cell-based VLSI design J Monteiro, JL Güntzel, L Agostini 2011 18th IEEE International Conference on Electronics, Circuits, and …, 2011 | 28 | 2011 |
| Drive strength aware cell movement techniques for timing driven placement G Flach, M Fogaça, J Monteiro, M Johann, R Reis Proceedings of the 2016 on International Symposium on Physical Design, 73-80, 2016 | 25 | 2016 |
| Quadratic timing objectives for incremental timing-driven placement optimization M Fogaça, G Flach, J Monteiro, M Johann, R Reis 2016 IEEE International Conference on Electronics, Circuits and Systems …, 2016 | 10 | 2016 |
| An incremental timing-driven flow using quadratic formulation for detailed placement G Flach, J Monteiro, M Fogaça, J Puget, P Butzen, M Johann, R Reis 2015 IFIP/IEEE International Conference on Very Large Scale Integration …, 2015 | 6 | 2015 |
| Routing-aware incremental timing-driven placement J Monteiro, NK Darav, G Flach, M Fogaça, R Reis, A Kennings, M Johann, ... 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 290-295, 2016 | 4 | 2016 |
| An analytical timing-driven algorithm for detailed placement J Monteiro, G Flach, M Johann, JLA Güntzel 2015 IEEE 6th Latin American Symposium on Circuits & Systems (LASCAS), 1-4, 2015 | 3 | 2015 |
| Cell-Based VLSI Implementations of the Add One Carry Select Adder J Monteiro, PV Campos, JL Güntzel, L Agostini SIM, 2011 | 3 | 2011 |
| Algorithms to improve area density utilization, routability and timing during detailed placement and legalization of VLSI circuits J Monteiro Universidade Federal do Rio Grande do Sul, 2019 | 2 | 2019 |
| An optimized cost flow algorithm to spread cells in detailed placement J Monteiro, M Johann, L Behjat ACM Transactions on Design Automation of Electronic Systems (TODAES) 24 (3 …, 2019 | 2 | 2019 |
| Algoritmo de posicionamento analítico-detalhado guiado a caminhos críticos JL Monteiro Universidade Federal do Rio Grande do Sul, 2014 | 2 | 2014 |
| Hierarchical Add One Carry Select Adder: Um Somador Select-Adder com Cadeia de Carry Logarítmica JL Monteiro | 1 | 2010 |
| VLSI Placement Optimization Algorithms J Monteiro Journal of Integrated Circuits and Systems 17 (3), 1-15, 2022 | | 2022 |
| A1CSAH: um Somador Rápido de Alta Eficiência Energética J Monteiro, L Agostini, JL Güntzell Anais do XXXI Concurso de Trabalhos de Iniciação Científica da SBC, 1-10, 2012 | | 2012 |
| Uma Arquitetura Rápida de Somador Binário de Alta Eficiência Energética JL Monteiro, LV Agostini, JLA Güntzel Revista Eletrônica de Iniciação Científica em Computação 12 (3), 2012 | | 2012 |
| Rsyn–A Physical Synthesis Framework for Research and Education M Fogaça, J Monteiro, M Johann, R Reis | | |
| Aatreyi Bal Abhranil Maiti Andrea Calimera Ao Ren A Roohi, A Yasin, A Bose, A Aysu, AF Tabrizi, B Behazin, B Liang, B Li, ... | | |
| Parthasarathy, Ananthanarayanan 274 Paul, Sudipta 7 Poncino, Massimo 57 Pravadelli, Graziano 246, 325 Puget, Julia J Hu, Y Huang, X Iturbe, MK Jaiswal, M Jayakrishnan, K Jelemenska, ... | | |
| A1CSA: A Low-Cost and Energy-Efficient Fast Adder Architecture Targeting Cell-Based VLSI Design J Monteiro, PP Campos, JL Güntzel, L Agostini | | |
| Um método criptografico utilizando geometria analıtica-Cifra de Hill JPP Flor, JL Monteiro, S Hebeda | | |
Marcelo JohannProfessor of Computer Science, UFRGSVerified email at inf.ufrgs.br
