Debora Matos
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Reconfigurable routers for low power and high performance
D Matos, C Concatto, M Kreutz, F Kastensmidt, L Carro, A Susin
IEEE Transactions on very large scale integration (VLSI) systems 19 (11 …, 2010
A new reconfigurable clock-gating technique for low power SRAM-based FPGAs
L Sterpone, L Carro, D Matos, S Wong, F Fakhar
2011 Design, Automation & Test in Europe, 1-6, 2011
Fault tolerant mechanism to improve yield in NoCs using a reconfigurable router
C Concatto, D Matos, L Carro, F Kastensmidt, A Susin, E Cota, M Kreutz
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System …, 2009
Noc power optimization using a reconfigurable router
C Concatto, D Matos, L Carro, F Kastensmidt, A Susin, M Kreutz
2009 IEEE Computer Society Annual Symposium on VLSI, 235-240, 2009
Multicore SIMD ASIP for next-generation sequencing and alignment biochip platforms
N Neves, N Sebastião, D Matos, P Tomás, P Flores, N Roma
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (7 …, 2014
A “deeper” look at detecting cyberbullying in social networks
H Rosa, D Matos, R Ribeiro, L Coheur, JP Carvalho
2018 International Joint Conference on Neural Networks (IJCNN), 1-8, 2018
Adaptive router architecture based on traffic behavior observability
D Matos, C Concatto, A Kologeski, L Carro, F Kastensmidt, A Susin, ...
2009 2nd International Workshop on Network on Chip Architectures, 17-22, 2009
Performance evaluation of hierarchical NoC topologies for stacked 3D ICs
D Matos, M Prass, M Kreutz, L Carro, A Susin
2015 IEEE International Symposium on Circuits and Systems (ISCAS), 1961-1964, 2015
BioBlaze: Multi-core SIMD ASIP for DNA sequence alignment
N Neves, N Sebastiao, A Patricio, D Matos, P Tomás, P Flores, N Roma
2013 IEEE 24th International Conference on Application-Specific Systems …, 2013
Floorplanning-aware design space exploration for application-specific hierarchical networks on-chip
D Matos, G Palermo, V Zaccaria, C Reinbrecht, A Susin, C Silvano, ...
Proceedings of the 4th International Workshop on Network on Chip …, 2011
Network interface to synchronize multiple packets on NoC-based systems-on-chip
D Matos, M Costa, L Carro, A Susin
2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, 31-36, 2010
Measuring the performance of a location-aware text prediction system
LF Garcia, LCD Oliveira, DMD Matos
ACM Transactions on Accessible Computing (TACCESS) 7 (1), 1-29, 2015
Event-based summarization using a centrality-as-relevance model
L Marujo, R Ribeiro, A Gershman, DM de Matos, JP Neto, J Carbonell
Knowledge and Information Systems 50 (3), 945-968, 2017
Multiple Hypothesis Tracking in camera networks
DM Antunes, D Figueira, DM Matos, A Bernardino, J Gaspar
2011 IEEE International Conference on Computer Vision Workshops (ICCV …, 2011
Spatial role labeling with convolutional neural networks
A Mazalov, B Martins, D Matos
Proceedings of the 9th Workshop on Geographic Information Retrieval, 1-7, 2015
Combining fault tolerance and serialization effort to improve yield in 3D Networks-on-Chip
A Kologeski, C Concatto, D Matos, D Grehs, T Motta, F Almeida, ...
2013 IEEE 20th International Conference on Electronics, Circuits, and …, 2013
ERA–Embedded Reconfigurable Architectures
S Wong, L Carro, M Rutzig, DM Matos, R Giorgi, N Puzovic, S Kaxiras, ...
Reconfigurable Computing, 239-259, 2011
Floorplan-aware hierarchical NoC topology with GALS interfaces
D Matos, C Reinbrecht, G Palermo, J Martinelli, A Susin, C Silvano, ...
2012 IEEE International Symposium on Circuits and Systems, 652-655, 2012
A NOC closed-loop performance monitor and adapter
D Matos, C Concatto, A Kologeski, L Carro, M Kreutz, F Kastensmidt, ...
Microprocessors and Microsystems 37 (6-7), 661-671, 2013
Recognition of named-event passages in news articles
L Marujo, W Ling, A Gershman, J Carbonell, JP Neto, D Matos
arXiv preprint arXiv:1306.4908, 2013
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