Jin Hu
Jin Hu
IBM, Michigan
Verified email at umich.edu
Title
Cited by
Cited by
Year
VLSI physical design: from graph partitioning to timing closure
AB Kahng, J Lienig, IL Markov, J Hu
Springer Science & Business Media, 2011
3202011
Vicis: A reliable network for unreliable silicon
D Fick, A DeOrio, J Hu, V Bertacco, D Blaauw, D Sylvester
Proceedings of the 46th Annual Design Automation Conference, 812-817, 2009
2352009
Progress and challenges in VLSI placement research
IL Markov, J Hu, MC Kim
Proceedings of the IEEE 103 (11), 1985-2003, 2015
1162015
A reliable routing architecture and algorithm for NoCs
A DeOrio, D Fick, V Bertacco, D Sylvester, D Blaauw, J Hu, G Chen
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012
1152012
A SimPLR method for routability-driven placement
MC Kim, J Hu, DJ Lee, IL Markov
2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 67-73, 2011
982011
Completing high-quality global routes
J Hu, JA Roy, IL Markov
Proceedings of the 19th international symposium on Physical design, 35-41, 2010
812010
ICCAD-2015 CAD contest in incremental timing-driven placement and benchmark suite
MC Kim, J Hu, J Li, N Viswanathan
2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 921-926, 2015
622015
Sensitivity-guided metaheuristics for accurate discrete gate sizing
J Hu, AB Kahng, SH Kang, MC Kim, IL Markov
Proceedings of the International Conference on Computer-Aided Design, 233-239, 2012
582012
Low-leakage flip-flops based on dual-threshold and multiple leakage reduction techniques
W Zhang, L Su, Y Zhang, L Li, J Hu
Journal of Circuits, Systems, and Computers 20 (01), 147-162, 2011
282011
Sidewinder: a scalable ILP-based router
J Hu, JA Roy, IL Markov
Proceedings of the 2008 international workshop on System level interconnect …, 2008
272008
TAU 2014 contest on removing common path pessimism during timing analysis
J Hu, D Sinha, I Keller
Proceedings of the 2014 on International Symposium on physical design, 153-160, 2014
212014
TAU 2014 contest on removing common path pessimism during timing analysis
J Hu, D Sinha, I Keller
Proceedings of the 2014 on International Symposium on physical design, 153-160, 2014
212014
TAU 2015 contest on incremental timing analysis
J Hu, G Schaeffer, V Garg
2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 882-889, 2015
202015
Taming the complexity of coordinated place and route
J Hu, MC Kim, IL Markov
2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC), 1-7, 2013
192013
Global and detailed placement
AB Kahng, J Lienig, IL Markov, J Hu
VLSI Physical Design: From Graph Partitioning to Timing Closure, 93-128, 2011
52011
Statistical timing using macro-model considering statistical timing value entry
J Hu, SSK Raghunathan, D Sinha, VP Zolotov
US Patent 9,798,843, 2017
32017
High-performance Global Routing for Trillion-gate Systems-on-Chips.
J Hu
32013
Timing closure
AB Kahng, J Lienig, IL Markov, J Hu
VLSI Physical Design: From Graph Partitioning to Timing Closure, 219-264, 2011
32011
TAU 2014 contest on removing common path pessimism during timing analysis: Special session paper: Common path pessimism removal (CPPR)
J Hu, D Sinha, I Keller
2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 591-591, 2014
22014
Netlist and system partitioning
AB Kahng, J Lienig, IL Markov, J Hu
VLSI Physical Design: From Graph Partitioning to Timing Closure, 31-54, 2011
22011
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