Squigulator: Simulation of nanopore sequencing signal data with tunable noise parameters H Gamaarachchi, JM Ferguson, H Samarakoon, K Liyanage, IW Deveson bioRxiv, 2023.05. 09.539953, 2023 | 7 | 2023 |
Cross layer design using HW/SW co-design and HLS to accelerate chaining in genomic analysis K Liyanage, H Gamaarachchi, R Ragel, S Parameswaran IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023 | 6 | 2023 |
Technique for Vendor and Device Agnostic Hardware Area-Time Estimation D Wijesundera, K Shah, K Liyanage, A Prakash, T Srikanthan, T Perera Applied Reconfigurable Computing. Architectures, Tools, and Applications …, 2020 | 2 | 2020 |
Interactive visualisation of raw nanopore signal data with Squigualiser H Samarakoon, K Liyanage, JM Ferguson, S Parameswaran, ... Biorxiv, 2024.02. 19.581111, 2024 | 1 | 2024 |
Efficient end-to-end long-read sequence mapping using minimap2-fpga integrated with hardware accelerated chaining K Liyanage, H Samarakoon, S Parameswaran, H Gamaarachchi Scientific Reports 13 (1), 20174, 2023 | | 2023 |
Algorithms and Architectures for Accelerating Long Read Sequence Analysis H Gamaarachchi, K Liyanage, S Parameswaran 2023 60th ACM/IEEE Design Automation Conference (DAC), 1-4, 2023 | | 2023 |
minimap2-fpga: Integrating hardware-accelerated chaining for efficient end-to-end long-read sequence mapping K Liyanage, H Samarakoon, S Parameswaran, H Gamaarachchi bioRxiv, 2023.05. 30.542681, 2023 | | 2023 |
An Iterative Technique for Runtime Efficient Hardware-Software Partitioning D Wijesundera, K Liyanage, A Prakash, T Srikanthan, T Perera 2019 International Conference on Field-Programmable Technology (ICFPT), 403-406, 2019 | | 2019 |