Johannes Partzsch
Johannes Partzsch
Chair for Highly Parallel VLSI Systems and Neuromorphic Circuits, TU Dresden
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A comprehensive workflow for general-purpose neural modeling with highly configurable neuromorphic hardware systems
D Brüderle, MA Petrovici, B Vogginger, M Ehrlich, T Pfeil, S Millner, ...
Biological cybernetics 104 (4-5), 263-296, 2011
Neuromorphic hardware in the loop: Training a deep spiking network on the brainscales wafer-scale system
S Schmitt, J Klähn, G Bellec, A Grübl, M Guettler, A Hartel, S Hartmann, ...
2017 International Joint Conference on Neural Networks (IJCNN), 2227-2234, 2017
A biological-realtime neuromorphic system in 28 nm CMOS using low-leakage switched capacitor circuits
C Mayr, J Partzsch, M Noack, S Hänzsche, S Scholze, S Höppner, ...
IEEE transactions on biomedical circuits and systems 10 (1), 243-254, 2015
Live demonstration: A scaled-down version of the BrainScaleS wafer-scale neuromorphic system
J Schemmel, A Grübl, S Hartmann, A Kononov, C Mayr, K Meier, S Millner, ...
Circuits and Systems (ISCAS), 2012 IEEE International Symposium on, 702-702, 2012
A 32GBit/s communication SoC for a waferscale neuromorphic system
S Scholze, H Eisenreich, S Höppner, G Ellguth, S Henker, M Ander, ...
Integration, the VLSI Journal 45 (1), 61-75, 2012
Rate and pulse based plasticity governed by local synaptic state variables
CG Mayr, J Partzsch
Frontiers in synaptic neuroscience 2, 2010
Memory-efficient Deep Learning on a SpiNNaker 2 prototype
C Liu, G Bellec, B Vogginger, D Kappel, J Partzsch, F Neumärker, ...
Frontiers in neuroscience 12, 2018
VLSI implementation of a 2.8 Gevent/s packet-based AER interface with routing and event sorting functionality
S Scholze, S Schiefer, J Partzsch, S Hartmann, CG Mayr, S Höppner, ...
Frontiers in neuroscience 5, 2011
Analyzing the scaling of connectivity in neuromorphic hardware and in models of neural networks
J Partzsch, R Schüffny
Neural Networks, IEEE Transactions on 22 (6), 919-935, 2011
Switched-capacitor realization of presynaptic short-term-plasticity and stop-learning synapses in 28 nm CMOS
M Noack, J Partzsch, CG Mayr, S Hänzsche, S Scholze, S Höppner, ...
Frontiers in neuroscience 9, 10, 2015
Waveform driven plasticity in BiFeO3 memristive devices: model and implementation
C Mayr, P Stärke, J Partzsch, L Cederstroem, R Schüffny, Y Shuai, N Du, ...
Advances in Neural Information Processing Systems, 1700-1708, 2012
A fixed point exponential function accelerator for a neuromorphic many-core system
J Partzsch, S Höppner, M Eberlein, R Schüffny, C Mayr, DR Lester, ...
Circuits and Systems (ISCAS), 2017 IEEE International Symposium on, 1-4, 2017
Efficient reward-based structural plasticity on a SpiNNaker 2 prototype
Y Yan, D Kappel, F Neumärker, J Partzsch, B Vogginger, S Höppner, ...
IEEE transactions on biomedical circuits and systems 13 (3), 579-591, 2019
Highly integrated packet-based AER communication infrastructure with 3Gevent/s throughput
S Hartmann, S Schiefer, S Scholze, J Partzsch, C Mayr, S Henker, ...
Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International …, 2010
Reducing the computational footprint for real-time BCPNN learning
B Vogginger, R Schüffny, A Lansner, L Cederström, J Partzsch, ...
Name: Frontiers in Neuroscience 9 (2), 2015
Replicating experimental spike and rate based neural learning in CMOS
C Mayr, M Noack, J Partzsch, R Schüffny
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International …, 2010
Accuracy evaluation of numerical methods used in state-of-the-art simulators for spiking neural networks
S Henker, J Partzsch, R Schüffny
Journal of computational neuroscience 32 (2), 309-326, 2012
Biology-derived synaptic dynamics and optimized system architecture for neuromorphic hardware
M Noack, J Partzsch, C Mayr, S Henker, R Schüffny
Mixed Design of Integrated Circuits and Systems (MIXDES), 2010 Proceedings …, 2010
Dynamic voltage and frequency scaling for neuromorphic many-core systems
S Höppner, Y Yan, B Vogginger, A Dixius, J Partzsch, F Neumärker, ...
2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017
VLSI implementation of a conductance-based multi-synapse using switched-capacitor circuits
M Noack, M Krause, C Mayr, J Partzsch, R Schuffny
Circuits and Systems (ISCAS), 2014 IEEE International Symposium on, 850-853, 2014
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