Patrick Girard
Patrick Girard
Verified email at lirmm.fr - Homepage
Title
Cited by
Cited by
Year
Survey of low-power testing of VLSI circuits
P Girard
IEEE Design & test of computers 19 (3), 82-92, 2002
5992002
Observation of exclusive deeply virtual compton scattering in polarized electron beam asymmetry measurements
S Stepanyan, VD Burkert, L Elouadrhiri, GS Adams, E Anciant, ...
Physical Review Letters 87 (18), 182002, 2001
4622001
Power-aware testing and test strategies for low power devices
P Girard, N Nicolici, X Wen
Springer Science & Business Media, 2010
2422010
A test vector inhibiting technique for low energy BIST design
P Girard, L Guiller, C Landrault, S Pravossoudovitch
Proceedings 17th IEEE VLSI Test Symposium (Cat. No. PR00146), 407-412, 1999
2191999
A gated clock scheme for low power scan testing of logic ICs or embedded cores
Y Bonhomme, P Girard, L Guiller, C Landrault, S Pravossoudovitch
Proceedings 10th Asian Test Symposium, 253-258, 2001
1872001
A modified clock scheme for a low power BIST test pattern generator
P Girard, L Guiller, C Landrault, S Pravossoudovitch, HJ Wunderlich
Proceedings 19th IEEE VLSI Test Symposium. VTS 2001, 306-311, 2001
1842001
Reduction of power consumption during test application by test vector ordering [VLSI circuits]
P Girard, C Landrault, S Pravossoudovitch, D Severac
Electronics Letters 33 (21), 1752-1754, 1997
1651997
Power driven chaining of flip-flops in scan architectures
Y Bonhomme, P Girard, C Landrault, S Pravossoudovitch
Proceedings. International Test Conference, 796-803, 2002
1332002
Low power testing of VLSI circuits: Problems and solutions
P Girard
Proceedings IEEE 2000 First International Symposium on Quality Electronic …, 2000
1142000
A test vector ordering technique for switching activity reduction during test operation
P Girard, L Guiller, C Landrault, S Pravossoudovitch
Proceedings Ninth Great Lakes Symposium on VLSI, 24-27, 1999
1081999
Low-energy BIST design: Impact of the LFSR TPG parameters on the weighted switching activity
P Girard, L Guiller, C Landrault, S Pravossoudovitch, J Figueras, ...
1999 IEEE International Symposium on Circuits and Systems (ISCAS) 1, 110-113, 1999
961999
Low power BIST by filtering non-detecting vectors
S Manich, A Gabarro, M Lopez, J Figueras, P Girard, L Guiller, ...
Journal of Electronic Testing 16 (3), 193-202, 2000
942000
Efficient scan chain design for power minimization during scan testing under routing constraint
Y Bonhomme, P Girard, L Guiller, C Landrault, S Pravossoudovitch
ITC: International Test Conference, 488-493, 2003
912003
Circuit partitioning for low power BIST design with minimized peak power consumption
P Girard, L Guiller, C Landrault, S Pravossoudovitch
Proceedings Eighth Asian Test Symposium (ATS'99), 89-94, 1999
851999
A novel scheme to reduce power supply noise for high-quality at-speed scan testing
X Wen, K Miyase, S Kajihara, T Suzuki, Y Yamato, P Girard, Y Ohsumi, ...
2007 IEEE International Test Conference, 1-10, 2007
832007
An optimized BIST test pattern generator for delay testing
P Girard, C Landrault, V Moreda, S Pravossoudovitch
Proceedings. 15th IEEE VLSI Test Symposium (Cat. No. 97TB100125), 94-100, 1997
791997
A study of tapered 3-D TSVs for power and thermal integrity
A Todri, S Kundu, P Girard, A Bosio, L Dilillo, A Virazel
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (2), 306-319, 2012
772012
Dynamic Read Destructive Faults in Embedded-SRAMs: Analysis and March Test Solution
L Dilillo, P Girard, S Pravossoudovitch, A Virazel, S Borri, M Hage-Hassan
ETS: European Test Symposium, 140-145, 2004
752004
Advanced test methods for SRAMs: effective solutions for dynamic fault detection in nanoscaled technologies
A Bosio, L Dilillo, P Girard, S Pravossoudovitch, A Virazel
Springer Science & Business Media, 2009
74*2009
On calculating efficient LFSR seeds for built-in self test
C Fagot, O Gascuel, P Girard, C Landrault
European Test Workshop 1999 (Cat. No. PR00390), 7-14, 1999
701999
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