| ENGN: A high-throughput and energy-efficient accelerator for large graph neural networks S Liang, Y Wang, C Liu, L He, LI Huawei, D Xu, X Li IEEE Transactions on Computers, 2020 | 195 | 2020 |
| A survey on graph processing accelerators: Challenges and opportunities CY Gui, L Zheng, B He, C Liu, XY Chen, XF Liao, H Jin Journal of Computer Science and Technology 34, 339-371, 2019 | 97 | 2019 |
| Vertical interconnects squeezing in symmetric 3D mesh Network-on-Chip C Liu, L Zhang, Y Han, X Li 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), 357-362, 2011 | 82 | 2011 |
| Linear Symmetric Quantization of Neural Networks for Low-precision Integer Hardware X Zhao, Y Wang, X Cai, C Liu, L Zhang International Conference on Learning Representations (ICLR), 2020 | 77 | 2020 |
| QuickDough: A rapid FPGA loop accelerator design framework using soft CGRA overlay C Liu, HC Ng, HKH So 2015 International Conference on Field Programmable Technology (FPT), 56-63, 2015 | 68 | 2015 |
| Network-aware locality scheduling for distributed data operators in data centers L Cheng, Y Wang, Q Liu, DHJ Epema, C Liu, Y Mao, J Murphy IEEE Transactions on Parallel and Distributed Systems 32 (6), 1494-1510, 2021 | 55 | 2021 |
| Deepburning-gl: an automated framework for generating graph neural network accelerators S Liang, C Liu, Y Wang, H Li, X Li Proceedings of the 39th International Conference on Computer-Aided Design, 1-9, 2020 | 44 | 2020 |
| Reliability Evaluation and Analysis of FPGA-Based Neural Network Acceleration System D Xu, Z Zhu, C Liu, Y Wang, S Zhao, L Zhang, H Liang, H Li, KT Cheng IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2021 | 42 | 2021 |
| NISAR: An AXI compliant on-chip NI architecture offering transaction reordering processing X Yang, Z Qing-li, F Fang-fa, Y Ming-yan, L Cheng 2007 7th International Conference on ASIC, 890-893, 2007 | 39 | 2007 |
| FCN-engine: Accelerating deconvolutional layers in classic CNN processors D Xu, K Tu, Y Wang, C Liu, B He, H Li 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-6, 2018 | 38 | 2018 |
| A resilient on-chip router design through data path salvaging C Liu, L Zhang, Y Han, X Li 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), 437-442, 2011 | 38 | 2011 |
| FPGA overlays HKH So, C Liu FPGAs for Software Programmers, 285-305, 2016 | 37 | 2016 |
| Automatic nested loop acceleration on FPGAs using soft CGRA overlay C Liu, HC Ng, HKH So arXiv preprint arXiv:1509.00042, 2015 | 36 | 2015 |
| Economizing TSV Resources in 3-D Network-on-Chip Design Y Wang, YH Han, L Zhang, BZ Fu, C Liu, HW Li, X Li IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1-13, 2014 | 36 | 2014 |
| {GLIST}: Towards {in-storage} graph learning C Li, Y Wang, C Liu, S Liang, H Li, X Li 2021 USENIX Annual Technical Conference (USENIX ATC 21), 225-238, 2021 | 35 | 2021 |
| HyCA: A hybrid computing architecture for fault-tolerant deep learning C Liu, C Chu, D Xu, Y Wang, Q Wang, H Li, X Li, KT Cheng IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021 | 28 | 2021 |
| BitPruner: Network pruning for bit-serial accelerators X Zhao, Y Wang, C Liu, C Shi, K Tu, L Zhang 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 28 | 2020 |
| Resilient neural network training for accelerators with computing errors D Xu, K Xing, C Liu, Y Wang, Y Dai, L Cheng, H Li, L Zhang 2019 IEEE 30th International Conference on Application-specific Systems …, 2019 | 26* | 2019 |
| A soft processor overlay with tightly-coupled FPGA accelerator HC Ng, C Liu, HKH So arXiv preprint arXiv:1606.06483, 2016 | 26 | 2016 |
| You Only Search Once: A Fast Automation Framework for Single-Stage DNN/Accelerator Co-design W Chen, Y Wang, S Yang, C Liu, L Zhang 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2020 | 25 | 2020 |
Ying WangInstitute of Computing Technology, Chinese Academy of SciencesVerified email at ict.ac.cn
